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https://github.com/edk2-porting/linux-next.git
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6710247706
This write_page() function is functionally equivalent to the default in nand_base.c. Its only difference is in subpage programming support, which cafe_nand.c does not advertise, so the difference is negligible. Signed-off-by: Brian Norris <computersforpeace@gmail.com>
870 lines
24 KiB
C
870 lines
24 KiB
C
/*
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* Driver for One Laptop Per Child ‘CAFÉ’ controller, aka Marvell 88ALP01
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*
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* The data sheet for this device can be found at:
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* http://wiki.laptop.org/go/Datasheets
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*
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* Copyright © 2006 Red Hat, Inc.
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* Copyright © 2006 David Woodhouse <dwmw2@infradead.org>
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*/
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#define DEBUG
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#include <linux/device.h>
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#undef DEBUG
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#include <linux/mtd/mtd.h>
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#include <linux/mtd/nand.h>
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#include <linux/mtd/partitions.h>
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#include <linux/rslib.h>
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#include <linux/pci.h>
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#include <linux/delay.h>
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#include <linux/interrupt.h>
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#include <linux/dma-mapping.h>
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#include <linux/slab.h>
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#include <linux/module.h>
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#include <asm/io.h>
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#define CAFE_NAND_CTRL1 0x00
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#define CAFE_NAND_CTRL2 0x04
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#define CAFE_NAND_CTRL3 0x08
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#define CAFE_NAND_STATUS 0x0c
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#define CAFE_NAND_IRQ 0x10
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#define CAFE_NAND_IRQ_MASK 0x14
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#define CAFE_NAND_DATA_LEN 0x18
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#define CAFE_NAND_ADDR1 0x1c
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#define CAFE_NAND_ADDR2 0x20
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#define CAFE_NAND_TIMING1 0x24
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#define CAFE_NAND_TIMING2 0x28
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#define CAFE_NAND_TIMING3 0x2c
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#define CAFE_NAND_NONMEM 0x30
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#define CAFE_NAND_ECC_RESULT 0x3C
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#define CAFE_NAND_DMA_CTRL 0x40
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#define CAFE_NAND_DMA_ADDR0 0x44
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#define CAFE_NAND_DMA_ADDR1 0x48
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#define CAFE_NAND_ECC_SYN01 0x50
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#define CAFE_NAND_ECC_SYN23 0x54
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#define CAFE_NAND_ECC_SYN45 0x58
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#define CAFE_NAND_ECC_SYN67 0x5c
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#define CAFE_NAND_READ_DATA 0x1000
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#define CAFE_NAND_WRITE_DATA 0x2000
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#define CAFE_GLOBAL_CTRL 0x3004
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#define CAFE_GLOBAL_IRQ 0x3008
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#define CAFE_GLOBAL_IRQ_MASK 0x300c
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#define CAFE_NAND_RESET 0x3034
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/* Missing from the datasheet: bit 19 of CTRL1 sets CE0 vs. CE1 */
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#define CTRL1_CHIPSELECT (1<<19)
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struct cafe_priv {
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struct nand_chip nand;
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struct pci_dev *pdev;
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void __iomem *mmio;
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struct rs_control *rs;
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uint32_t ctl1;
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uint32_t ctl2;
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int datalen;
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int nr_data;
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int data_pos;
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int page_addr;
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dma_addr_t dmaaddr;
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unsigned char *dmabuf;
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};
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static int usedma = 1;
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module_param(usedma, int, 0644);
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static int skipbbt = 0;
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module_param(skipbbt, int, 0644);
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static int debug = 0;
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module_param(debug, int, 0644);
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static int regdebug = 0;
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module_param(regdebug, int, 0644);
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static int checkecc = 1;
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module_param(checkecc, int, 0644);
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static unsigned int numtimings;
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static int timing[3];
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module_param_array(timing, int, &numtimings, 0644);
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static const char *part_probes[] = { "cmdlinepart", "RedBoot", NULL };
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/* Hrm. Why isn't this already conditional on something in the struct device? */
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#define cafe_dev_dbg(dev, args...) do { if (debug) dev_dbg(dev, ##args); } while(0)
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/* Make it easier to switch to PIO if we need to */
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#define cafe_readl(cafe, addr) readl((cafe)->mmio + CAFE_##addr)
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#define cafe_writel(cafe, datum, addr) writel(datum, (cafe)->mmio + CAFE_##addr)
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static int cafe_device_ready(struct mtd_info *mtd)
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{
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struct cafe_priv *cafe = mtd->priv;
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int result = !!(cafe_readl(cafe, NAND_STATUS) & 0x40000000);
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uint32_t irqs = cafe_readl(cafe, NAND_IRQ);
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cafe_writel(cafe, irqs, NAND_IRQ);
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cafe_dev_dbg(&cafe->pdev->dev, "NAND device is%s ready, IRQ %x (%x) (%x,%x)\n",
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result?"":" not", irqs, cafe_readl(cafe, NAND_IRQ),
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cafe_readl(cafe, GLOBAL_IRQ), cafe_readl(cafe, GLOBAL_IRQ_MASK));
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return result;
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}
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static void cafe_write_buf(struct mtd_info *mtd, const uint8_t *buf, int len)
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{
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struct cafe_priv *cafe = mtd->priv;
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if (usedma)
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memcpy(cafe->dmabuf + cafe->datalen, buf, len);
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else
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memcpy_toio(cafe->mmio + CAFE_NAND_WRITE_DATA + cafe->datalen, buf, len);
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cafe->datalen += len;
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cafe_dev_dbg(&cafe->pdev->dev, "Copy 0x%x bytes to write buffer. datalen 0x%x\n",
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len, cafe->datalen);
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}
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static void cafe_read_buf(struct mtd_info *mtd, uint8_t *buf, int len)
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{
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struct cafe_priv *cafe = mtd->priv;
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if (usedma)
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memcpy(buf, cafe->dmabuf + cafe->datalen, len);
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else
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memcpy_fromio(buf, cafe->mmio + CAFE_NAND_READ_DATA + cafe->datalen, len);
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cafe_dev_dbg(&cafe->pdev->dev, "Copy 0x%x bytes from position 0x%x in read buffer.\n",
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len, cafe->datalen);
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cafe->datalen += len;
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}
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static uint8_t cafe_read_byte(struct mtd_info *mtd)
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{
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struct cafe_priv *cafe = mtd->priv;
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uint8_t d;
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cafe_read_buf(mtd, &d, 1);
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cafe_dev_dbg(&cafe->pdev->dev, "Read %02x\n", d);
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return d;
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}
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static void cafe_nand_cmdfunc(struct mtd_info *mtd, unsigned command,
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int column, int page_addr)
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{
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struct cafe_priv *cafe = mtd->priv;
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int adrbytes = 0;
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uint32_t ctl1;
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uint32_t doneint = 0x80000000;
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cafe_dev_dbg(&cafe->pdev->dev, "cmdfunc %02x, 0x%x, 0x%x\n",
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command, column, page_addr);
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if (command == NAND_CMD_ERASE2 || command == NAND_CMD_PAGEPROG) {
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/* Second half of a command we already calculated */
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cafe_writel(cafe, cafe->ctl2 | 0x100 | command, NAND_CTRL2);
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ctl1 = cafe->ctl1;
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cafe->ctl2 &= ~(1<<30);
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cafe_dev_dbg(&cafe->pdev->dev, "Continue command, ctl1 %08x, #data %d\n",
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cafe->ctl1, cafe->nr_data);
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goto do_command;
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}
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/* Reset ECC engine */
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cafe_writel(cafe, 0, NAND_CTRL2);
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/* Emulate NAND_CMD_READOOB on large-page chips */
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if (mtd->writesize > 512 &&
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command == NAND_CMD_READOOB) {
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column += mtd->writesize;
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command = NAND_CMD_READ0;
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}
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/* FIXME: Do we need to send read command before sending data
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for small-page chips, to position the buffer correctly? */
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if (column != -1) {
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cafe_writel(cafe, column, NAND_ADDR1);
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adrbytes = 2;
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if (page_addr != -1)
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goto write_adr2;
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} else if (page_addr != -1) {
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cafe_writel(cafe, page_addr & 0xffff, NAND_ADDR1);
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page_addr >>= 16;
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write_adr2:
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cafe_writel(cafe, page_addr, NAND_ADDR2);
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adrbytes += 2;
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if (mtd->size > mtd->writesize << 16)
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adrbytes++;
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}
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cafe->data_pos = cafe->datalen = 0;
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/* Set command valid bit, mask in the chip select bit */
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ctl1 = 0x80000000 | command | (cafe->ctl1 & CTRL1_CHIPSELECT);
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/* Set RD or WR bits as appropriate */
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if (command == NAND_CMD_READID || command == NAND_CMD_STATUS) {
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ctl1 |= (1<<26); /* rd */
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/* Always 5 bytes, for now */
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cafe->datalen = 4;
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/* And one address cycle -- even for STATUS, since the controller doesn't work without */
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adrbytes = 1;
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} else if (command == NAND_CMD_READ0 || command == NAND_CMD_READ1 ||
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command == NAND_CMD_READOOB || command == NAND_CMD_RNDOUT) {
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ctl1 |= 1<<26; /* rd */
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/* For now, assume just read to end of page */
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cafe->datalen = mtd->writesize + mtd->oobsize - column;
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} else if (command == NAND_CMD_SEQIN)
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ctl1 |= 1<<25; /* wr */
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/* Set number of address bytes */
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if (adrbytes)
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ctl1 |= ((adrbytes-1)|8) << 27;
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if (command == NAND_CMD_SEQIN || command == NAND_CMD_ERASE1) {
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/* Ignore the first command of a pair; the hardware
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deals with them both at once, later */
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cafe->ctl1 = ctl1;
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cafe_dev_dbg(&cafe->pdev->dev, "Setup for delayed command, ctl1 %08x, dlen %x\n",
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cafe->ctl1, cafe->datalen);
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return;
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}
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/* RNDOUT and READ0 commands need a following byte */
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if (command == NAND_CMD_RNDOUT)
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cafe_writel(cafe, cafe->ctl2 | 0x100 | NAND_CMD_RNDOUTSTART, NAND_CTRL2);
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else if (command == NAND_CMD_READ0 && mtd->writesize > 512)
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cafe_writel(cafe, cafe->ctl2 | 0x100 | NAND_CMD_READSTART, NAND_CTRL2);
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do_command:
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cafe_dev_dbg(&cafe->pdev->dev, "dlen %x, ctl1 %x, ctl2 %x\n",
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cafe->datalen, ctl1, cafe_readl(cafe, NAND_CTRL2));
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/* NB: The datasheet lies -- we really should be subtracting 1 here */
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cafe_writel(cafe, cafe->datalen, NAND_DATA_LEN);
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cafe_writel(cafe, 0x90000000, NAND_IRQ);
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if (usedma && (ctl1 & (3<<25))) {
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uint32_t dmactl = 0xc0000000 + cafe->datalen;
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/* If WR or RD bits set, set up DMA */
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if (ctl1 & (1<<26)) {
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/* It's a read */
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dmactl |= (1<<29);
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/* ... so it's done when the DMA is done, not just
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the command. */
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doneint = 0x10000000;
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}
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cafe_writel(cafe, dmactl, NAND_DMA_CTRL);
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}
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cafe->datalen = 0;
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if (unlikely(regdebug)) {
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int i;
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printk("About to write command %08x to register 0\n", ctl1);
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for (i=4; i< 0x5c; i+=4)
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printk("Register %x: %08x\n", i, readl(cafe->mmio + i));
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}
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cafe_writel(cafe, ctl1, NAND_CTRL1);
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/* Apply this short delay always to ensure that we do wait tWB in
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* any case on any machine. */
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ndelay(100);
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if (1) {
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int c;
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uint32_t irqs;
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for (c = 500000; c != 0; c--) {
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irqs = cafe_readl(cafe, NAND_IRQ);
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if (irqs & doneint)
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break;
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udelay(1);
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if (!(c % 100000))
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cafe_dev_dbg(&cafe->pdev->dev, "Wait for ready, IRQ %x\n", irqs);
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cpu_relax();
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}
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cafe_writel(cafe, doneint, NAND_IRQ);
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cafe_dev_dbg(&cafe->pdev->dev, "Command %x completed after %d usec, irqs %x (%x)\n",
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command, 500000-c, irqs, cafe_readl(cafe, NAND_IRQ));
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}
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WARN_ON(cafe->ctl2 & (1<<30));
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switch (command) {
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case NAND_CMD_CACHEDPROG:
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case NAND_CMD_PAGEPROG:
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case NAND_CMD_ERASE1:
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case NAND_CMD_ERASE2:
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case NAND_CMD_SEQIN:
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case NAND_CMD_RNDIN:
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case NAND_CMD_STATUS:
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case NAND_CMD_RNDOUT:
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cafe_writel(cafe, cafe->ctl2, NAND_CTRL2);
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return;
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}
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nand_wait_ready(mtd);
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cafe_writel(cafe, cafe->ctl2, NAND_CTRL2);
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}
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static void cafe_select_chip(struct mtd_info *mtd, int chipnr)
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{
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struct cafe_priv *cafe = mtd->priv;
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cafe_dev_dbg(&cafe->pdev->dev, "select_chip %d\n", chipnr);
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/* Mask the appropriate bit into the stored value of ctl1
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which will be used by cafe_nand_cmdfunc() */
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if (chipnr)
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cafe->ctl1 |= CTRL1_CHIPSELECT;
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else
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cafe->ctl1 &= ~CTRL1_CHIPSELECT;
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}
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static irqreturn_t cafe_nand_interrupt(int irq, void *id)
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{
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struct mtd_info *mtd = id;
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struct cafe_priv *cafe = mtd->priv;
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uint32_t irqs = cafe_readl(cafe, NAND_IRQ);
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cafe_writel(cafe, irqs & ~0x90000000, NAND_IRQ);
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if (!irqs)
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return IRQ_NONE;
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cafe_dev_dbg(&cafe->pdev->dev, "irq, bits %x (%x)\n", irqs, cafe_readl(cafe, NAND_IRQ));
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return IRQ_HANDLED;
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}
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static void cafe_nand_bug(struct mtd_info *mtd)
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{
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BUG();
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}
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static int cafe_nand_write_oob(struct mtd_info *mtd,
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struct nand_chip *chip, int page)
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{
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int status = 0;
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chip->cmdfunc(mtd, NAND_CMD_SEQIN, mtd->writesize, page);
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chip->write_buf(mtd, chip->oob_poi, mtd->oobsize);
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chip->cmdfunc(mtd, NAND_CMD_PAGEPROG, -1, -1);
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status = chip->waitfunc(mtd, chip);
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return status & NAND_STATUS_FAIL ? -EIO : 0;
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}
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/* Don't use -- use nand_read_oob_std for now */
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static int cafe_nand_read_oob(struct mtd_info *mtd, struct nand_chip *chip,
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int page)
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{
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chip->cmdfunc(mtd, NAND_CMD_READOOB, 0, page);
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chip->read_buf(mtd, chip->oob_poi, mtd->oobsize);
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return 0;
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}
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/**
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* cafe_nand_read_page_syndrome - [REPLACEABLE] hardware ecc syndrome based page read
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* @mtd: mtd info structure
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* @chip: nand chip info structure
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* @buf: buffer to store read data
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* @oob_required: caller expects OOB data read to chip->oob_poi
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*
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* The hw generator calculates the error syndrome automatically. Therefore
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* we need a special oob layout and handling.
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*/
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static int cafe_nand_read_page(struct mtd_info *mtd, struct nand_chip *chip,
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uint8_t *buf, int oob_required, int page)
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{
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struct cafe_priv *cafe = mtd->priv;
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unsigned int max_bitflips = 0;
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cafe_dev_dbg(&cafe->pdev->dev, "ECC result %08x SYN1,2 %08x\n",
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cafe_readl(cafe, NAND_ECC_RESULT),
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cafe_readl(cafe, NAND_ECC_SYN01));
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chip->read_buf(mtd, buf, mtd->writesize);
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chip->read_buf(mtd, chip->oob_poi, mtd->oobsize);
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if (checkecc && cafe_readl(cafe, NAND_ECC_RESULT) & (1<<18)) {
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unsigned short syn[8], pat[4];
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int pos[4];
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u8 *oob = chip->oob_poi;
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int i, n;
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for (i=0; i<8; i+=2) {
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uint32_t tmp = cafe_readl(cafe, NAND_ECC_SYN01 + (i*2));
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syn[i] = cafe->rs->index_of[tmp & 0xfff];
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syn[i+1] = cafe->rs->index_of[(tmp >> 16) & 0xfff];
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}
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n = decode_rs16(cafe->rs, NULL, NULL, 1367, syn, 0, pos, 0,
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pat);
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for (i = 0; i < n; i++) {
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int p = pos[i];
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/* The 12-bit symbols are mapped to bytes here */
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if (p > 1374) {
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/* out of range */
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n = -1374;
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} else if (p == 0) {
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/* high four bits do not correspond to data */
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if (pat[i] > 0xff)
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n = -2048;
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else
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buf[0] ^= pat[i];
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} else if (p == 1365) {
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buf[2047] ^= pat[i] >> 4;
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oob[0] ^= pat[i] << 4;
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} else if (p > 1365) {
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if ((p & 1) == 1) {
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oob[3*p/2 - 2048] ^= pat[i] >> 4;
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oob[3*p/2 - 2047] ^= pat[i] << 4;
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} else {
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oob[3*p/2 - 2049] ^= pat[i] >> 8;
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oob[3*p/2 - 2048] ^= pat[i];
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}
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} else if ((p & 1) == 1) {
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buf[3*p/2] ^= pat[i] >> 4;
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buf[3*p/2 + 1] ^= pat[i] << 4;
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} else {
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buf[3*p/2 - 1] ^= pat[i] >> 8;
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buf[3*p/2] ^= pat[i];
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}
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}
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if (n < 0) {
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dev_dbg(&cafe->pdev->dev, "Failed to correct ECC at %08x\n",
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cafe_readl(cafe, NAND_ADDR2) * 2048);
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for (i = 0; i < 0x5c; i += 4)
|
||
printk("Register %x: %08x\n", i, readl(cafe->mmio + i));
|
||
mtd->ecc_stats.failed++;
|
||
} else {
|
||
dev_dbg(&cafe->pdev->dev, "Corrected %d symbol errors\n", n);
|
||
mtd->ecc_stats.corrected += n;
|
||
max_bitflips = max_t(unsigned int, max_bitflips, n);
|
||
}
|
||
}
|
||
|
||
return max_bitflips;
|
||
}
|
||
|
||
static struct nand_ecclayout cafe_oobinfo_2048 = {
|
||
.eccbytes = 14,
|
||
.eccpos = { 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13},
|
||
.oobfree = {{14, 50}}
|
||
};
|
||
|
||
/* Ick. The BBT code really ought to be able to work this bit out
|
||
for itself from the above, at least for the 2KiB case */
|
||
static uint8_t cafe_bbt_pattern_2048[] = { 'B', 'b', 't', '0' };
|
||
static uint8_t cafe_mirror_pattern_2048[] = { '1', 't', 'b', 'B' };
|
||
|
||
static uint8_t cafe_bbt_pattern_512[] = { 0xBB };
|
||
static uint8_t cafe_mirror_pattern_512[] = { 0xBC };
|
||
|
||
|
||
static struct nand_bbt_descr cafe_bbt_main_descr_2048 = {
|
||
.options = NAND_BBT_LASTBLOCK | NAND_BBT_CREATE | NAND_BBT_WRITE
|
||
| NAND_BBT_2BIT | NAND_BBT_VERSION,
|
||
.offs = 14,
|
||
.len = 4,
|
||
.veroffs = 18,
|
||
.maxblocks = 4,
|
||
.pattern = cafe_bbt_pattern_2048
|
||
};
|
||
|
||
static struct nand_bbt_descr cafe_bbt_mirror_descr_2048 = {
|
||
.options = NAND_BBT_LASTBLOCK | NAND_BBT_CREATE | NAND_BBT_WRITE
|
||
| NAND_BBT_2BIT | NAND_BBT_VERSION,
|
||
.offs = 14,
|
||
.len = 4,
|
||
.veroffs = 18,
|
||
.maxblocks = 4,
|
||
.pattern = cafe_mirror_pattern_2048
|
||
};
|
||
|
||
static struct nand_ecclayout cafe_oobinfo_512 = {
|
||
.eccbytes = 14,
|
||
.eccpos = { 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13},
|
||
.oobfree = {{14, 2}}
|
||
};
|
||
|
||
static struct nand_bbt_descr cafe_bbt_main_descr_512 = {
|
||
.options = NAND_BBT_LASTBLOCK | NAND_BBT_CREATE | NAND_BBT_WRITE
|
||
| NAND_BBT_2BIT | NAND_BBT_VERSION,
|
||
.offs = 14,
|
||
.len = 1,
|
||
.veroffs = 15,
|
||
.maxblocks = 4,
|
||
.pattern = cafe_bbt_pattern_512
|
||
};
|
||
|
||
static struct nand_bbt_descr cafe_bbt_mirror_descr_512 = {
|
||
.options = NAND_BBT_LASTBLOCK | NAND_BBT_CREATE | NAND_BBT_WRITE
|
||
| NAND_BBT_2BIT | NAND_BBT_VERSION,
|
||
.offs = 14,
|
||
.len = 1,
|
||
.veroffs = 15,
|
||
.maxblocks = 4,
|
||
.pattern = cafe_mirror_pattern_512
|
||
};
|
||
|
||
|
||
static int cafe_nand_write_page_lowlevel(struct mtd_info *mtd,
|
||
struct nand_chip *chip,
|
||
const uint8_t *buf, int oob_required)
|
||
{
|
||
struct cafe_priv *cafe = mtd->priv;
|
||
|
||
chip->write_buf(mtd, buf, mtd->writesize);
|
||
chip->write_buf(mtd, chip->oob_poi, mtd->oobsize);
|
||
|
||
/* Set up ECC autogeneration */
|
||
cafe->ctl2 |= (1<<30);
|
||
|
||
return 0;
|
||
}
|
||
|
||
static int cafe_nand_block_bad(struct mtd_info *mtd, loff_t ofs, int getchip)
|
||
{
|
||
return 0;
|
||
}
|
||
|
||
/* F_2[X]/(X**6+X+1) */
|
||
static unsigned short gf64_mul(u8 a, u8 b)
|
||
{
|
||
u8 c;
|
||
unsigned int i;
|
||
|
||
c = 0;
|
||
for (i = 0; i < 6; i++) {
|
||
if (a & 1)
|
||
c ^= b;
|
||
a >>= 1;
|
||
b <<= 1;
|
||
if ((b & 0x40) != 0)
|
||
b ^= 0x43;
|
||
}
|
||
|
||
return c;
|
||
}
|
||
|
||
/* F_64[X]/(X**2+X+A**-1) with A the generator of F_64[X] */
|
||
static u16 gf4096_mul(u16 a, u16 b)
|
||
{
|
||
u8 ah, al, bh, bl, ch, cl;
|
||
|
||
ah = a >> 6;
|
||
al = a & 0x3f;
|
||
bh = b >> 6;
|
||
bl = b & 0x3f;
|
||
|
||
ch = gf64_mul(ah ^ al, bh ^ bl) ^ gf64_mul(al, bl);
|
||
cl = gf64_mul(gf64_mul(ah, bh), 0x21) ^ gf64_mul(al, bl);
|
||
|
||
return (ch << 6) ^ cl;
|
||
}
|
||
|
||
static int cafe_mul(int x)
|
||
{
|
||
if (x == 0)
|
||
return 1;
|
||
return gf4096_mul(x, 0xe01);
|
||
}
|
||
|
||
static int cafe_nand_probe(struct pci_dev *pdev,
|
||
const struct pci_device_id *ent)
|
||
{
|
||
struct mtd_info *mtd;
|
||
struct cafe_priv *cafe;
|
||
uint32_t ctrl;
|
||
int err = 0;
|
||
int old_dma;
|
||
struct nand_buffers *nbuf;
|
||
|
||
/* Very old versions shared the same PCI ident for all three
|
||
functions on the chip. Verify the class too... */
|
||
if ((pdev->class >> 8) != PCI_CLASS_MEMORY_FLASH)
|
||
return -ENODEV;
|
||
|
||
err = pci_enable_device(pdev);
|
||
if (err)
|
||
return err;
|
||
|
||
pci_set_master(pdev);
|
||
|
||
mtd = kzalloc(sizeof(*mtd) + sizeof(struct cafe_priv), GFP_KERNEL);
|
||
if (!mtd)
|
||
return -ENOMEM;
|
||
cafe = (void *)(&mtd[1]);
|
||
|
||
mtd->dev.parent = &pdev->dev;
|
||
mtd->priv = cafe;
|
||
mtd->owner = THIS_MODULE;
|
||
|
||
cafe->pdev = pdev;
|
||
cafe->mmio = pci_iomap(pdev, 0, 0);
|
||
if (!cafe->mmio) {
|
||
dev_warn(&pdev->dev, "failed to iomap\n");
|
||
err = -ENOMEM;
|
||
goto out_free_mtd;
|
||
}
|
||
|
||
cafe->rs = init_rs_non_canonical(12, &cafe_mul, 0, 1, 8);
|
||
if (!cafe->rs) {
|
||
err = -ENOMEM;
|
||
goto out_ior;
|
||
}
|
||
|
||
cafe->nand.cmdfunc = cafe_nand_cmdfunc;
|
||
cafe->nand.dev_ready = cafe_device_ready;
|
||
cafe->nand.read_byte = cafe_read_byte;
|
||
cafe->nand.read_buf = cafe_read_buf;
|
||
cafe->nand.write_buf = cafe_write_buf;
|
||
cafe->nand.select_chip = cafe_select_chip;
|
||
|
||
cafe->nand.chip_delay = 0;
|
||
|
||
/* Enable the following for a flash based bad block table */
|
||
cafe->nand.bbt_options = NAND_BBT_USE_FLASH;
|
||
cafe->nand.options = NAND_OWN_BUFFERS;
|
||
|
||
if (skipbbt) {
|
||
cafe->nand.options |= NAND_SKIP_BBTSCAN;
|
||
cafe->nand.block_bad = cafe_nand_block_bad;
|
||
}
|
||
|
||
if (numtimings && numtimings != 3) {
|
||
dev_warn(&cafe->pdev->dev, "%d timing register values ignored; precisely three are required\n", numtimings);
|
||
}
|
||
|
||
if (numtimings == 3) {
|
||
cafe_dev_dbg(&cafe->pdev->dev, "Using provided timings (%08x %08x %08x)\n",
|
||
timing[0], timing[1], timing[2]);
|
||
} else {
|
||
timing[0] = cafe_readl(cafe, NAND_TIMING1);
|
||
timing[1] = cafe_readl(cafe, NAND_TIMING2);
|
||
timing[2] = cafe_readl(cafe, NAND_TIMING3);
|
||
|
||
if (timing[0] | timing[1] | timing[2]) {
|
||
cafe_dev_dbg(&cafe->pdev->dev, "Timing registers already set (%08x %08x %08x)\n",
|
||
timing[0], timing[1], timing[2]);
|
||
} else {
|
||
dev_warn(&cafe->pdev->dev, "Timing registers unset; using most conservative defaults\n");
|
||
timing[0] = timing[1] = timing[2] = 0xffffffff;
|
||
}
|
||
}
|
||
|
||
/* Start off by resetting the NAND controller completely */
|
||
cafe_writel(cafe, 1, NAND_RESET);
|
||
cafe_writel(cafe, 0, NAND_RESET);
|
||
|
||
cafe_writel(cafe, timing[0], NAND_TIMING1);
|
||
cafe_writel(cafe, timing[1], NAND_TIMING2);
|
||
cafe_writel(cafe, timing[2], NAND_TIMING3);
|
||
|
||
cafe_writel(cafe, 0xffffffff, NAND_IRQ_MASK);
|
||
err = request_irq(pdev->irq, &cafe_nand_interrupt, IRQF_SHARED,
|
||
"CAFE NAND", mtd);
|
||
if (err) {
|
||
dev_warn(&pdev->dev, "Could not register IRQ %d\n", pdev->irq);
|
||
goto out_ior;
|
||
}
|
||
|
||
/* Disable master reset, enable NAND clock */
|
||
ctrl = cafe_readl(cafe, GLOBAL_CTRL);
|
||
ctrl &= 0xffffeff0;
|
||
ctrl |= 0x00007000;
|
||
cafe_writel(cafe, ctrl | 0x05, GLOBAL_CTRL);
|
||
cafe_writel(cafe, ctrl | 0x0a, GLOBAL_CTRL);
|
||
cafe_writel(cafe, 0, NAND_DMA_CTRL);
|
||
|
||
cafe_writel(cafe, 0x7006, GLOBAL_CTRL);
|
||
cafe_writel(cafe, 0x700a, GLOBAL_CTRL);
|
||
|
||
/* Enable NAND IRQ in global IRQ mask register */
|
||
cafe_writel(cafe, 0x80000007, GLOBAL_IRQ_MASK);
|
||
cafe_dev_dbg(&cafe->pdev->dev, "Control %x, IRQ mask %x\n",
|
||
cafe_readl(cafe, GLOBAL_CTRL),
|
||
cafe_readl(cafe, GLOBAL_IRQ_MASK));
|
||
|
||
/* Do not use the DMA for the nand_scan_ident() */
|
||
old_dma = usedma;
|
||
usedma = 0;
|
||
|
||
/* Scan to find existence of the device */
|
||
if (nand_scan_ident(mtd, 2, NULL)) {
|
||
err = -ENXIO;
|
||
goto out_irq;
|
||
}
|
||
|
||
cafe->dmabuf = dma_alloc_coherent(&cafe->pdev->dev,
|
||
2112 + sizeof(struct nand_buffers) +
|
||
mtd->writesize + mtd->oobsize,
|
||
&cafe->dmaaddr, GFP_KERNEL);
|
||
if (!cafe->dmabuf) {
|
||
err = -ENOMEM;
|
||
goto out_irq;
|
||
}
|
||
cafe->nand.buffers = nbuf = (void *)cafe->dmabuf + 2112;
|
||
|
||
/* Set up DMA address */
|
||
cafe_writel(cafe, cafe->dmaaddr & 0xffffffff, NAND_DMA_ADDR0);
|
||
if (sizeof(cafe->dmaaddr) > 4)
|
||
/* Shift in two parts to shut the compiler up */
|
||
cafe_writel(cafe, (cafe->dmaaddr >> 16) >> 16, NAND_DMA_ADDR1);
|
||
else
|
||
cafe_writel(cafe, 0, NAND_DMA_ADDR1);
|
||
|
||
cafe_dev_dbg(&cafe->pdev->dev, "Set DMA address to %x (virt %p)\n",
|
||
cafe_readl(cafe, NAND_DMA_ADDR0), cafe->dmabuf);
|
||
|
||
/* this driver does not need the @ecccalc and @ecccode */
|
||
nbuf->ecccalc = NULL;
|
||
nbuf->ecccode = NULL;
|
||
nbuf->databuf = (uint8_t *)(nbuf + 1);
|
||
|
||
/* Restore the DMA flag */
|
||
usedma = old_dma;
|
||
|
||
cafe->ctl2 = 1<<27; /* Reed-Solomon ECC */
|
||
if (mtd->writesize == 2048)
|
||
cafe->ctl2 |= 1<<29; /* 2KiB page size */
|
||
|
||
/* Set up ECC according to the type of chip we found */
|
||
if (mtd->writesize == 2048) {
|
||
cafe->nand.ecc.layout = &cafe_oobinfo_2048;
|
||
cafe->nand.bbt_td = &cafe_bbt_main_descr_2048;
|
||
cafe->nand.bbt_md = &cafe_bbt_mirror_descr_2048;
|
||
} else if (mtd->writesize == 512) {
|
||
cafe->nand.ecc.layout = &cafe_oobinfo_512;
|
||
cafe->nand.bbt_td = &cafe_bbt_main_descr_512;
|
||
cafe->nand.bbt_md = &cafe_bbt_mirror_descr_512;
|
||
} else {
|
||
printk(KERN_WARNING "Unexpected NAND flash writesize %d. Aborting\n",
|
||
mtd->writesize);
|
||
goto out_free_dma;
|
||
}
|
||
cafe->nand.ecc.mode = NAND_ECC_HW_SYNDROME;
|
||
cafe->nand.ecc.size = mtd->writesize;
|
||
cafe->nand.ecc.bytes = 14;
|
||
cafe->nand.ecc.strength = 4;
|
||
cafe->nand.ecc.hwctl = (void *)cafe_nand_bug;
|
||
cafe->nand.ecc.calculate = (void *)cafe_nand_bug;
|
||
cafe->nand.ecc.correct = (void *)cafe_nand_bug;
|
||
cafe->nand.ecc.write_page = cafe_nand_write_page_lowlevel;
|
||
cafe->nand.ecc.write_oob = cafe_nand_write_oob;
|
||
cafe->nand.ecc.read_page = cafe_nand_read_page;
|
||
cafe->nand.ecc.read_oob = cafe_nand_read_oob;
|
||
|
||
err = nand_scan_tail(mtd);
|
||
if (err)
|
||
goto out_free_dma;
|
||
|
||
pci_set_drvdata(pdev, mtd);
|
||
|
||
mtd->name = "cafe_nand";
|
||
mtd_device_parse_register(mtd, part_probes, NULL, NULL, 0);
|
||
|
||
goto out;
|
||
|
||
out_free_dma:
|
||
dma_free_coherent(&cafe->pdev->dev,
|
||
2112 + sizeof(struct nand_buffers) +
|
||
mtd->writesize + mtd->oobsize,
|
||
cafe->dmabuf, cafe->dmaaddr);
|
||
out_irq:
|
||
/* Disable NAND IRQ in global IRQ mask register */
|
||
cafe_writel(cafe, ~1 & cafe_readl(cafe, GLOBAL_IRQ_MASK), GLOBAL_IRQ_MASK);
|
||
free_irq(pdev->irq, mtd);
|
||
out_ior:
|
||
pci_iounmap(pdev, cafe->mmio);
|
||
out_free_mtd:
|
||
kfree(mtd);
|
||
out:
|
||
return err;
|
||
}
|
||
|
||
static void cafe_nand_remove(struct pci_dev *pdev)
|
||
{
|
||
struct mtd_info *mtd = pci_get_drvdata(pdev);
|
||
struct cafe_priv *cafe = mtd->priv;
|
||
|
||
/* Disable NAND IRQ in global IRQ mask register */
|
||
cafe_writel(cafe, ~1 & cafe_readl(cafe, GLOBAL_IRQ_MASK), GLOBAL_IRQ_MASK);
|
||
free_irq(pdev->irq, mtd);
|
||
nand_release(mtd);
|
||
free_rs(cafe->rs);
|
||
pci_iounmap(pdev, cafe->mmio);
|
||
dma_free_coherent(&cafe->pdev->dev,
|
||
2112 + sizeof(struct nand_buffers) +
|
||
mtd->writesize + mtd->oobsize,
|
||
cafe->dmabuf, cafe->dmaaddr);
|
||
kfree(mtd);
|
||
}
|
||
|
||
static const struct pci_device_id cafe_nand_tbl[] = {
|
||
{ PCI_VENDOR_ID_MARVELL, PCI_DEVICE_ID_MARVELL_88ALP01_NAND,
|
||
PCI_ANY_ID, PCI_ANY_ID },
|
||
{ }
|
||
};
|
||
|
||
MODULE_DEVICE_TABLE(pci, cafe_nand_tbl);
|
||
|
||
static int cafe_nand_resume(struct pci_dev *pdev)
|
||
{
|
||
uint32_t ctrl;
|
||
struct mtd_info *mtd = pci_get_drvdata(pdev);
|
||
struct cafe_priv *cafe = mtd->priv;
|
||
|
||
/* Start off by resetting the NAND controller completely */
|
||
cafe_writel(cafe, 1, NAND_RESET);
|
||
cafe_writel(cafe, 0, NAND_RESET);
|
||
cafe_writel(cafe, 0xffffffff, NAND_IRQ_MASK);
|
||
|
||
/* Restore timing configuration */
|
||
cafe_writel(cafe, timing[0], NAND_TIMING1);
|
||
cafe_writel(cafe, timing[1], NAND_TIMING2);
|
||
cafe_writel(cafe, timing[2], NAND_TIMING3);
|
||
|
||
/* Disable master reset, enable NAND clock */
|
||
ctrl = cafe_readl(cafe, GLOBAL_CTRL);
|
||
ctrl &= 0xffffeff0;
|
||
ctrl |= 0x00007000;
|
||
cafe_writel(cafe, ctrl | 0x05, GLOBAL_CTRL);
|
||
cafe_writel(cafe, ctrl | 0x0a, GLOBAL_CTRL);
|
||
cafe_writel(cafe, 0, NAND_DMA_CTRL);
|
||
cafe_writel(cafe, 0x7006, GLOBAL_CTRL);
|
||
cafe_writel(cafe, 0x700a, GLOBAL_CTRL);
|
||
|
||
/* Set up DMA address */
|
||
cafe_writel(cafe, cafe->dmaaddr & 0xffffffff, NAND_DMA_ADDR0);
|
||
if (sizeof(cafe->dmaaddr) > 4)
|
||
/* Shift in two parts to shut the compiler up */
|
||
cafe_writel(cafe, (cafe->dmaaddr >> 16) >> 16, NAND_DMA_ADDR1);
|
||
else
|
||
cafe_writel(cafe, 0, NAND_DMA_ADDR1);
|
||
|
||
/* Enable NAND IRQ in global IRQ mask register */
|
||
cafe_writel(cafe, 0x80000007, GLOBAL_IRQ_MASK);
|
||
return 0;
|
||
}
|
||
|
||
static struct pci_driver cafe_nand_pci_driver = {
|
||
.name = "CAFÉ NAND",
|
||
.id_table = cafe_nand_tbl,
|
||
.probe = cafe_nand_probe,
|
||
.remove = cafe_nand_remove,
|
||
.resume = cafe_nand_resume,
|
||
};
|
||
|
||
module_pci_driver(cafe_nand_pci_driver);
|
||
|
||
MODULE_LICENSE("GPL");
|
||
MODULE_AUTHOR("David Woodhouse <dwmw2@infradead.org>");
|
||
MODULE_DESCRIPTION("NAND flash driver for OLPC CAFÉ chip");
|