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2f0d6f20ec
The following symbols are needlessly defined global: exynos4_verify_speed exynos4_getspeed exynos4_set_clkdiv Make them static. Signed-off-by: Axel Lin <axel.lin@gmail.com> Acked-by: Kukjin Kim <kgene.kim@samsung.com> Signed-off-by: Dave Jones <davej@redhat.com>
569 lines
14 KiB
C
569 lines
14 KiB
C
/*
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* Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
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* http://www.samsung.com
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*
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* EXYNOS4 - CPU frequency scaling support
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#include <linux/types.h>
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#include <linux/kernel.h>
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#include <linux/err.h>
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#include <linux/clk.h>
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#include <linux/io.h>
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#include <linux/slab.h>
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#include <linux/regulator/consumer.h>
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#include <linux/cpufreq.h>
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#include <mach/map.h>
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#include <mach/regs-clock.h>
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#include <mach/regs-mem.h>
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#include <plat/clock.h>
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#include <plat/pm.h>
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static struct clk *cpu_clk;
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static struct clk *moutcore;
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static struct clk *mout_mpll;
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static struct clk *mout_apll;
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static struct regulator *arm_regulator;
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static struct regulator *int_regulator;
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static struct cpufreq_freqs freqs;
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static unsigned int memtype;
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enum exynos4_memory_type {
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DDR2 = 4,
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LPDDR2,
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DDR3,
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};
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enum cpufreq_level_index {
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L0, L1, L2, L3, CPUFREQ_LEVEL_END,
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};
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static struct cpufreq_frequency_table exynos4_freq_table[] = {
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{L0, 1000*1000},
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{L1, 800*1000},
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{L2, 400*1000},
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{L3, 100*1000},
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{0, CPUFREQ_TABLE_END},
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};
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static unsigned int clkdiv_cpu0[CPUFREQ_LEVEL_END][7] = {
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/*
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* Clock divider value for following
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* { DIVCORE, DIVCOREM0, DIVCOREM1, DIVPERIPH,
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* DIVATB, DIVPCLK_DBG, DIVAPLL }
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*/
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/* ARM L0: 1000MHz */
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{ 0, 3, 7, 3, 3, 0, 1 },
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/* ARM L1: 800MHz */
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{ 0, 3, 7, 3, 3, 0, 1 },
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/* ARM L2: 400MHz */
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{ 0, 1, 3, 1, 3, 0, 1 },
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/* ARM L3: 100MHz */
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{ 0, 0, 1, 0, 3, 1, 1 },
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};
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static unsigned int clkdiv_cpu1[CPUFREQ_LEVEL_END][2] = {
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/*
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* Clock divider value for following
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* { DIVCOPY, DIVHPM }
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*/
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/* ARM L0: 1000MHz */
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{ 3, 0 },
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/* ARM L1: 800MHz */
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{ 3, 0 },
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/* ARM L2: 400MHz */
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{ 3, 0 },
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/* ARM L3: 100MHz */
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{ 3, 0 },
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};
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static unsigned int clkdiv_dmc0[CPUFREQ_LEVEL_END][8] = {
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/*
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* Clock divider value for following
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* { DIVACP, DIVACP_PCLK, DIVDPHY, DIVDMC, DIVDMCD
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* DIVDMCP, DIVCOPY2, DIVCORE_TIMERS }
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*/
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/* DMC L0: 400MHz */
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{ 3, 1, 1, 1, 1, 1, 3, 1 },
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/* DMC L1: 400MHz */
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{ 3, 1, 1, 1, 1, 1, 3, 1 },
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/* DMC L2: 266.7MHz */
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{ 7, 1, 1, 2, 1, 1, 3, 1 },
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/* DMC L3: 200MHz */
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{ 7, 1, 1, 3, 1, 1, 3, 1 },
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};
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static unsigned int clkdiv_top[CPUFREQ_LEVEL_END][5] = {
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/*
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* Clock divider value for following
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* { DIVACLK200, DIVACLK100, DIVACLK160, DIVACLK133, DIVONENAND }
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*/
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/* ACLK200 L0: 200MHz */
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{ 3, 7, 4, 5, 1 },
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/* ACLK200 L1: 200MHz */
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{ 3, 7, 4, 5, 1 },
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/* ACLK200 L2: 160MHz */
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{ 4, 7, 5, 7, 1 },
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/* ACLK200 L3: 133.3MHz */
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{ 5, 7, 7, 7, 1 },
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};
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static unsigned int clkdiv_lr_bus[CPUFREQ_LEVEL_END][2] = {
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/*
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* Clock divider value for following
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* { DIVGDL/R, DIVGPL/R }
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*/
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/* ACLK_GDL/R L0: 200MHz */
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{ 3, 1 },
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/* ACLK_GDL/R L1: 200MHz */
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{ 3, 1 },
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/* ACLK_GDL/R L2: 160MHz */
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{ 4, 1 },
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/* ACLK_GDL/R L3: 133.3MHz */
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{ 5, 1 },
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};
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struct cpufreq_voltage_table {
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unsigned int index; /* any */
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unsigned int arm_volt; /* uV */
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unsigned int int_volt;
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};
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static struct cpufreq_voltage_table exynos4_volt_table[CPUFREQ_LEVEL_END] = {
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{
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.index = L0,
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.arm_volt = 1200000,
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.int_volt = 1100000,
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}, {
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.index = L1,
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.arm_volt = 1100000,
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.int_volt = 1100000,
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}, {
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.index = L2,
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.arm_volt = 1000000,
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.int_volt = 1000000,
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}, {
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.index = L3,
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.arm_volt = 900000,
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.int_volt = 1000000,
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},
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};
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static unsigned int exynos4_apll_pms_table[CPUFREQ_LEVEL_END] = {
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/* APLL FOUT L0: 1000MHz */
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((250 << 16) | (6 << 8) | 1),
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/* APLL FOUT L1: 800MHz */
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((200 << 16) | (6 << 8) | 1),
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/* APLL FOUT L2 : 400MHz */
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((200 << 16) | (6 << 8) | 2),
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/* APLL FOUT L3: 100MHz */
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((200 << 16) | (6 << 8) | 4),
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};
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static int exynos4_verify_speed(struct cpufreq_policy *policy)
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{
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return cpufreq_frequency_table_verify(policy, exynos4_freq_table);
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}
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static unsigned int exynos4_getspeed(unsigned int cpu)
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{
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return clk_get_rate(cpu_clk) / 1000;
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}
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static void exynos4_set_clkdiv(unsigned int div_index)
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{
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unsigned int tmp;
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/* Change Divider - CPU0 */
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tmp = __raw_readl(S5P_CLKDIV_CPU);
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tmp &= ~(S5P_CLKDIV_CPU0_CORE_MASK | S5P_CLKDIV_CPU0_COREM0_MASK |
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S5P_CLKDIV_CPU0_COREM1_MASK | S5P_CLKDIV_CPU0_PERIPH_MASK |
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S5P_CLKDIV_CPU0_ATB_MASK | S5P_CLKDIV_CPU0_PCLKDBG_MASK |
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S5P_CLKDIV_CPU0_APLL_MASK);
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tmp |= ((clkdiv_cpu0[div_index][0] << S5P_CLKDIV_CPU0_CORE_SHIFT) |
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(clkdiv_cpu0[div_index][1] << S5P_CLKDIV_CPU0_COREM0_SHIFT) |
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(clkdiv_cpu0[div_index][2] << S5P_CLKDIV_CPU0_COREM1_SHIFT) |
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(clkdiv_cpu0[div_index][3] << S5P_CLKDIV_CPU0_PERIPH_SHIFT) |
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(clkdiv_cpu0[div_index][4] << S5P_CLKDIV_CPU0_ATB_SHIFT) |
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(clkdiv_cpu0[div_index][5] << S5P_CLKDIV_CPU0_PCLKDBG_SHIFT) |
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(clkdiv_cpu0[div_index][6] << S5P_CLKDIV_CPU0_APLL_SHIFT));
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__raw_writel(tmp, S5P_CLKDIV_CPU);
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do {
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tmp = __raw_readl(S5P_CLKDIV_STATCPU);
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} while (tmp & 0x1111111);
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/* Change Divider - CPU1 */
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tmp = __raw_readl(S5P_CLKDIV_CPU1);
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tmp &= ~((0x7 << 4) | 0x7);
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tmp |= ((clkdiv_cpu1[div_index][0] << 4) |
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(clkdiv_cpu1[div_index][1] << 0));
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__raw_writel(tmp, S5P_CLKDIV_CPU1);
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do {
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tmp = __raw_readl(S5P_CLKDIV_STATCPU1);
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} while (tmp & 0x11);
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/* Change Divider - DMC0 */
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tmp = __raw_readl(S5P_CLKDIV_DMC0);
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tmp &= ~(S5P_CLKDIV_DMC0_ACP_MASK | S5P_CLKDIV_DMC0_ACPPCLK_MASK |
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S5P_CLKDIV_DMC0_DPHY_MASK | S5P_CLKDIV_DMC0_DMC_MASK |
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S5P_CLKDIV_DMC0_DMCD_MASK | S5P_CLKDIV_DMC0_DMCP_MASK |
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S5P_CLKDIV_DMC0_COPY2_MASK | S5P_CLKDIV_DMC0_CORETI_MASK);
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tmp |= ((clkdiv_dmc0[div_index][0] << S5P_CLKDIV_DMC0_ACP_SHIFT) |
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(clkdiv_dmc0[div_index][1] << S5P_CLKDIV_DMC0_ACPPCLK_SHIFT) |
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(clkdiv_dmc0[div_index][2] << S5P_CLKDIV_DMC0_DPHY_SHIFT) |
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(clkdiv_dmc0[div_index][3] << S5P_CLKDIV_DMC0_DMC_SHIFT) |
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(clkdiv_dmc0[div_index][4] << S5P_CLKDIV_DMC0_DMCD_SHIFT) |
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(clkdiv_dmc0[div_index][5] << S5P_CLKDIV_DMC0_DMCP_SHIFT) |
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(clkdiv_dmc0[div_index][6] << S5P_CLKDIV_DMC0_COPY2_SHIFT) |
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(clkdiv_dmc0[div_index][7] << S5P_CLKDIV_DMC0_CORETI_SHIFT));
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__raw_writel(tmp, S5P_CLKDIV_DMC0);
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do {
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tmp = __raw_readl(S5P_CLKDIV_STAT_DMC0);
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} while (tmp & 0x11111111);
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/* Change Divider - TOP */
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tmp = __raw_readl(S5P_CLKDIV_TOP);
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tmp &= ~(S5P_CLKDIV_TOP_ACLK200_MASK | S5P_CLKDIV_TOP_ACLK100_MASK |
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S5P_CLKDIV_TOP_ACLK160_MASK | S5P_CLKDIV_TOP_ACLK133_MASK |
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S5P_CLKDIV_TOP_ONENAND_MASK);
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tmp |= ((clkdiv_top[div_index][0] << S5P_CLKDIV_TOP_ACLK200_SHIFT) |
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(clkdiv_top[div_index][1] << S5P_CLKDIV_TOP_ACLK100_SHIFT) |
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(clkdiv_top[div_index][2] << S5P_CLKDIV_TOP_ACLK160_SHIFT) |
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(clkdiv_top[div_index][3] << S5P_CLKDIV_TOP_ACLK133_SHIFT) |
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(clkdiv_top[div_index][4] << S5P_CLKDIV_TOP_ONENAND_SHIFT));
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__raw_writel(tmp, S5P_CLKDIV_TOP);
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do {
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tmp = __raw_readl(S5P_CLKDIV_STAT_TOP);
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} while (tmp & 0x11111);
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/* Change Divider - LEFTBUS */
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tmp = __raw_readl(S5P_CLKDIV_LEFTBUS);
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tmp &= ~(S5P_CLKDIV_BUS_GDLR_MASK | S5P_CLKDIV_BUS_GPLR_MASK);
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tmp |= ((clkdiv_lr_bus[div_index][0] << S5P_CLKDIV_BUS_GDLR_SHIFT) |
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(clkdiv_lr_bus[div_index][1] << S5P_CLKDIV_BUS_GPLR_SHIFT));
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__raw_writel(tmp, S5P_CLKDIV_LEFTBUS);
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do {
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tmp = __raw_readl(S5P_CLKDIV_STAT_LEFTBUS);
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} while (tmp & 0x11);
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/* Change Divider - RIGHTBUS */
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tmp = __raw_readl(S5P_CLKDIV_RIGHTBUS);
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tmp &= ~(S5P_CLKDIV_BUS_GDLR_MASK | S5P_CLKDIV_BUS_GPLR_MASK);
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tmp |= ((clkdiv_lr_bus[div_index][0] << S5P_CLKDIV_BUS_GDLR_SHIFT) |
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(clkdiv_lr_bus[div_index][1] << S5P_CLKDIV_BUS_GPLR_SHIFT));
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__raw_writel(tmp, S5P_CLKDIV_RIGHTBUS);
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do {
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tmp = __raw_readl(S5P_CLKDIV_STAT_RIGHTBUS);
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} while (tmp & 0x11);
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}
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static void exynos4_set_apll(unsigned int index)
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{
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unsigned int tmp;
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/* 1. MUX_CORE_SEL = MPLL, ARMCLK uses MPLL for lock time */
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clk_set_parent(moutcore, mout_mpll);
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do {
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tmp = (__raw_readl(S5P_CLKMUX_STATCPU)
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>> S5P_CLKSRC_CPU_MUXCORE_SHIFT);
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tmp &= 0x7;
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} while (tmp != 0x2);
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/* 2. Set APLL Lock time */
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__raw_writel(S5P_APLL_LOCKTIME, S5P_APLL_LOCK);
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/* 3. Change PLL PMS values */
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tmp = __raw_readl(S5P_APLL_CON0);
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tmp &= ~((0x3ff << 16) | (0x3f << 8) | (0x7 << 0));
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tmp |= exynos4_apll_pms_table[index];
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__raw_writel(tmp, S5P_APLL_CON0);
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/* 4. wait_lock_time */
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do {
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tmp = __raw_readl(S5P_APLL_CON0);
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} while (!(tmp & (0x1 << S5P_APLLCON0_LOCKED_SHIFT)));
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/* 5. MUX_CORE_SEL = APLL */
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clk_set_parent(moutcore, mout_apll);
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do {
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tmp = __raw_readl(S5P_CLKMUX_STATCPU);
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tmp &= S5P_CLKMUX_STATCPU_MUXCORE_MASK;
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} while (tmp != (0x1 << S5P_CLKSRC_CPU_MUXCORE_SHIFT));
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}
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static void exynos4_set_frequency(unsigned int old_index, unsigned int new_index)
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{
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unsigned int tmp;
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if (old_index > new_index) {
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/* The frequency changing to L0 needs to change apll */
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if (freqs.new == exynos4_freq_table[L0].frequency) {
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/* 1. Change the system clock divider values */
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exynos4_set_clkdiv(new_index);
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/* 2. Change the apll m,p,s value */
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exynos4_set_apll(new_index);
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} else {
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/* 1. Change the system clock divider values */
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exynos4_set_clkdiv(new_index);
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/* 2. Change just s value in apll m,p,s value */
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tmp = __raw_readl(S5P_APLL_CON0);
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tmp &= ~(0x7 << 0);
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tmp |= (exynos4_apll_pms_table[new_index] & 0x7);
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__raw_writel(tmp, S5P_APLL_CON0);
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}
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}
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else if (old_index < new_index) {
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/* The frequency changing from L0 needs to change apll */
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if (freqs.old == exynos4_freq_table[L0].frequency) {
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/* 1. Change the apll m,p,s value */
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exynos4_set_apll(new_index);
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/* 2. Change the system clock divider values */
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exynos4_set_clkdiv(new_index);
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} else {
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/* 1. Change just s value in apll m,p,s value */
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tmp = __raw_readl(S5P_APLL_CON0);
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tmp &= ~(0x7 << 0);
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tmp |= (exynos4_apll_pms_table[new_index] & 0x7);
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__raw_writel(tmp, S5P_APLL_CON0);
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/* 2. Change the system clock divider values */
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exynos4_set_clkdiv(new_index);
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}
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}
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}
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static int exynos4_target(struct cpufreq_policy *policy,
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unsigned int target_freq,
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unsigned int relation)
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{
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unsigned int index, old_index;
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unsigned int arm_volt, int_volt;
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freqs.old = exynos4_getspeed(policy->cpu);
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if (cpufreq_frequency_table_target(policy, exynos4_freq_table,
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freqs.old, relation, &old_index))
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return -EINVAL;
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if (cpufreq_frequency_table_target(policy, exynos4_freq_table,
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target_freq, relation, &index))
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return -EINVAL;
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freqs.new = exynos4_freq_table[index].frequency;
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freqs.cpu = policy->cpu;
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if (freqs.new == freqs.old)
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return 0;
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/* get the voltage value */
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arm_volt = exynos4_volt_table[index].arm_volt;
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int_volt = exynos4_volt_table[index].int_volt;
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cpufreq_notify_transition(&freqs, CPUFREQ_PRECHANGE);
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/* control regulator */
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if (freqs.new > freqs.old) {
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/* Voltage up */
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regulator_set_voltage(arm_regulator, arm_volt, arm_volt);
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regulator_set_voltage(int_regulator, int_volt, int_volt);
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}
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/* Clock Configuration Procedure */
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exynos4_set_frequency(old_index, index);
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/* control regulator */
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if (freqs.new < freqs.old) {
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/* Voltage down */
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regulator_set_voltage(arm_regulator, arm_volt, arm_volt);
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regulator_set_voltage(int_regulator, int_volt, int_volt);
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}
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cpufreq_notify_transition(&freqs, CPUFREQ_POSTCHANGE);
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return 0;
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}
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#ifdef CONFIG_PM
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static int exynos4_cpufreq_suspend(struct cpufreq_policy *policy)
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{
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return 0;
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}
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static int exynos4_cpufreq_resume(struct cpufreq_policy *policy)
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{
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return 0;
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}
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#endif
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static int exynos4_cpufreq_cpu_init(struct cpufreq_policy *policy)
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{
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policy->cur = policy->min = policy->max = exynos4_getspeed(policy->cpu);
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cpufreq_frequency_table_get_attr(exynos4_freq_table, policy->cpu);
|
|
|
|
/* set the transition latency value */
|
|
policy->cpuinfo.transition_latency = 100000;
|
|
|
|
/*
|
|
* EXYNOS4 multi-core processors has 2 cores
|
|
* that the frequency cannot be set independently.
|
|
* Each cpu is bound to the same speed.
|
|
* So the affected cpu is all of the cpus.
|
|
*/
|
|
cpumask_setall(policy->cpus);
|
|
|
|
return cpufreq_frequency_table_cpuinfo(policy, exynos4_freq_table);
|
|
}
|
|
|
|
static struct cpufreq_driver exynos4_driver = {
|
|
.flags = CPUFREQ_STICKY,
|
|
.verify = exynos4_verify_speed,
|
|
.target = exynos4_target,
|
|
.get = exynos4_getspeed,
|
|
.init = exynos4_cpufreq_cpu_init,
|
|
.name = "exynos4_cpufreq",
|
|
#ifdef CONFIG_PM
|
|
.suspend = exynos4_cpufreq_suspend,
|
|
.resume = exynos4_cpufreq_resume,
|
|
#endif
|
|
};
|
|
|
|
static int __init exynos4_cpufreq_init(void)
|
|
{
|
|
cpu_clk = clk_get(NULL, "armclk");
|
|
if (IS_ERR(cpu_clk))
|
|
return PTR_ERR(cpu_clk);
|
|
|
|
moutcore = clk_get(NULL, "moutcore");
|
|
if (IS_ERR(moutcore))
|
|
goto out;
|
|
|
|
mout_mpll = clk_get(NULL, "mout_mpll");
|
|
if (IS_ERR(mout_mpll))
|
|
goto out;
|
|
|
|
mout_apll = clk_get(NULL, "mout_apll");
|
|
if (IS_ERR(mout_apll))
|
|
goto out;
|
|
|
|
arm_regulator = regulator_get(NULL, "vdd_arm");
|
|
if (IS_ERR(arm_regulator)) {
|
|
printk(KERN_ERR "failed to get resource %s\n", "vdd_arm");
|
|
goto out;
|
|
}
|
|
|
|
int_regulator = regulator_get(NULL, "vdd_int");
|
|
if (IS_ERR(int_regulator)) {
|
|
printk(KERN_ERR "failed to get resource %s\n", "vdd_int");
|
|
goto out;
|
|
}
|
|
|
|
/*
|
|
* Check DRAM type.
|
|
* Because DVFS level is different according to DRAM type.
|
|
*/
|
|
memtype = __raw_readl(S5P_VA_DMC0 + S5P_DMC0_MEMCON_OFFSET);
|
|
memtype = (memtype >> S5P_DMC0_MEMTYPE_SHIFT);
|
|
memtype &= S5P_DMC0_MEMTYPE_MASK;
|
|
|
|
if ((memtype < DDR2) && (memtype > DDR3)) {
|
|
printk(KERN_ERR "%s: wrong memtype= 0x%x\n", __func__, memtype);
|
|
goto out;
|
|
} else {
|
|
printk(KERN_DEBUG "%s: memtype= 0x%x\n", __func__, memtype);
|
|
}
|
|
|
|
return cpufreq_register_driver(&exynos4_driver);
|
|
|
|
out:
|
|
if (!IS_ERR(cpu_clk))
|
|
clk_put(cpu_clk);
|
|
|
|
if (!IS_ERR(moutcore))
|
|
clk_put(moutcore);
|
|
|
|
if (!IS_ERR(mout_mpll))
|
|
clk_put(mout_mpll);
|
|
|
|
if (!IS_ERR(mout_apll))
|
|
clk_put(mout_apll);
|
|
|
|
if (!IS_ERR(arm_regulator))
|
|
regulator_put(arm_regulator);
|
|
|
|
if (!IS_ERR(int_regulator))
|
|
regulator_put(int_regulator);
|
|
|
|
printk(KERN_ERR "%s: failed initialization\n", __func__);
|
|
|
|
return -EINVAL;
|
|
}
|
|
late_initcall(exynos4_cpufreq_init);
|