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3e287bec6f
Re-jig the CPU abort helpers to take the PC/PSR in r4/r5 rather than r2/r3. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
34 lines
1023 B
ArmAsm
34 lines
1023 B
ArmAsm
#include <linux/linkage.h>
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#include <asm/assembler.h>
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#include "abort-macro.S"
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/*
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* Function: v5tj_early_abort
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*
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* Params : r4 = aborted context pc
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* : r5 = aborted context psr
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*
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* Returns : r0 = address of abort
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* : r1 = FSR, bit 11 = write
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* : r2-r8 = corrupted
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* : r9 = preserved
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* : sp = pointer to registers
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*
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* Purpose : obtain information about current aborted instruction.
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* Note: we read user space. This means we might cause a data
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* abort here if the I-TLB and D-TLB aren't seeing the same
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* picture. Unfortunately, this does happen. We live with it.
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*/
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.align 5
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ENTRY(v5tj_early_abort)
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mrc p15, 0, r1, c5, c0, 0 @ get FSR
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mrc p15, 0, r0, c6, c0, 0 @ get FAR
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bic r1, r1, #1 << 11 | 1 << 10 @ clear bits 11 and 10 of FSR
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tst r5, #PSR_J_BIT @ Java?
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movne pc, lr
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do_thumb_abort fsr=r1, pc=r4, psr=r5, tmp=r3
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ldreq r3, [r4] @ read aborted ARM instruction
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do_ldrd_abort tmp=r2, insn=r3
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tst r3, #1 << 20 @ L = 0 -> write
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orreq r1, r1, #1 << 11 @ yes.
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mov pc, lr
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