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067bb938da
This adds support for hdlc-bus mode to the fsl_ucc_hdlc driver. This can be enabled with the "fsl,hdlc-bus" property in the DTS node of the corresponding ucc. This aligns the configuration of the UPSMR and GUMR registers to what is done in our ucc_hdlc driver (that only support hdlc-bus mode) and with the QuickEngine's documentation for hdlc-bus mode. GUMR/SYNL is set to AUTO for the busmode as in this case the CD signal is ignored. The brkpt_support is enabled to set the HBM1 bit in the CMXUCR register to configure an open-drain connected HDLC bus. Signed-off-by: Holger Brunck <holger.brunck@keymile.com> Cc: Zhao Qiang <qiang.zhao@nxp.com> Signed-off-by: David S. Miller <davem@davemloft.net>
149 lines
3.1 KiB
C
149 lines
3.1 KiB
C
/* Freescale QUICC Engine HDLC Device Driver
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*
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* Copyright 2014 Freescale Semiconductor Inc.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License as published by the
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* Free Software Foundation; either version 2 of the License, or (at your
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* option) any later version.
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*/
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#ifndef _UCC_HDLC_H_
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#define _UCC_HDLC_H_
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#include <linux/kernel.h>
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#include <linux/list.h>
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#include <soc/fsl/qe/immap_qe.h>
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#include <soc/fsl/qe/qe.h>
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#include <soc/fsl/qe/ucc.h>
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#include <soc/fsl/qe/ucc_fast.h>
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/* UCC HDLC event register */
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#define UCCE_HDLC_RX_EVENTS \
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(UCC_HDLC_UCCE_RXF | UCC_HDLC_UCCE_RXB | UCC_HDLC_UCCE_BSY)
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#define UCCE_HDLC_TX_EVENTS (UCC_HDLC_UCCE_TXB | UCC_HDLC_UCCE_TXE)
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struct ucc_hdlc_param {
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__be16 riptr;
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__be16 tiptr;
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__be16 res0;
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__be16 mrblr;
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__be32 rstate;
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__be32 rbase;
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__be16 rbdstat;
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__be16 rbdlen;
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__be32 rdptr;
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__be32 tstate;
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__be32 tbase;
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__be16 tbdstat;
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__be16 tbdlen;
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__be32 tdptr;
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__be32 rbptr;
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__be32 tbptr;
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__be32 rcrc;
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__be32 res1;
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__be32 tcrc;
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__be32 res2;
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__be32 res3;
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__be32 c_mask;
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__be32 c_pres;
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__be16 disfc;
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__be16 crcec;
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__be16 abtsc;
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__be16 nmarc;
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__be32 max_cnt;
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__be16 mflr;
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__be16 rfthr;
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__be16 rfcnt;
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__be16 hmask;
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__be16 haddr1;
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__be16 haddr2;
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__be16 haddr3;
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__be16 haddr4;
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__be16 ts_tmp;
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__be16 tmp_mb;
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};
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struct ucc_hdlc_private {
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struct ucc_tdm *utdm;
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struct ucc_tdm_info *ut_info;
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struct ucc_fast_private *uccf;
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struct device *dev;
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struct net_device *ndev;
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struct napi_struct napi;
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struct ucc_fast __iomem *uf_regs; /* UCC Fast registers */
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struct ucc_hdlc_param __iomem *ucc_pram;
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u16 tsa;
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bool hdlc_busy;
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bool loopback;
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bool hdlc_bus;
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u8 *tx_buffer;
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u8 *rx_buffer;
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dma_addr_t dma_tx_addr;
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dma_addr_t dma_rx_addr;
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struct qe_bd *tx_bd_base;
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struct qe_bd *rx_bd_base;
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dma_addr_t dma_tx_bd;
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dma_addr_t dma_rx_bd;
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struct qe_bd *curtx_bd;
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struct qe_bd *currx_bd;
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struct qe_bd *dirty_tx;
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u16 currx_bdnum;
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struct sk_buff **tx_skbuff;
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struct sk_buff **rx_skbuff;
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u16 skb_curtx;
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u16 skb_currx;
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unsigned short skb_dirtytx;
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unsigned short tx_ring_size;
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unsigned short rx_ring_size;
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u32 ucc_pram_offset;
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unsigned short encoding;
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unsigned short parity;
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u32 clocking;
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spinlock_t lock; /* lock for Tx BD and Tx buffer */
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#ifdef CONFIG_PM
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struct ucc_hdlc_param *ucc_pram_bak;
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u32 gumr;
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u8 guemr;
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u32 cmxsi1cr_l, cmxsi1cr_h;
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u32 cmxsi1syr;
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u32 cmxucr[4];
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#endif
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};
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#define TX_BD_RING_LEN 0x10
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#define RX_BD_RING_LEN 0x20
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#define RX_CLEAN_MAX 0x10
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#define NUM_OF_BUF 4
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#define MAX_RX_BUF_LENGTH (48 * 0x20)
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#define MAX_FRAME_LENGTH (MAX_RX_BUF_LENGTH + 8)
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#define ALIGNMENT_OF_UCC_HDLC_PRAM 64
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#define SI_BANK_SIZE 128
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#define MAX_HDLC_NUM 4
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#define HDLC_HEAD_LEN 2
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#define HDLC_CRC_SIZE 2
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#define TX_RING_MOD_MASK(size) (size - 1)
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#define RX_RING_MOD_MASK(size) (size - 1)
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#define HDLC_HEAD_MASK 0x0000
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#define DEFAULT_HDLC_HEAD 0xff44
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#define DEFAULT_ADDR_MASK 0x00ff
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#define DEFAULT_HDLC_ADDR 0x00ff
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#define BMR_GBL 0x20000000
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#define BMR_BIG_ENDIAN 0x10000000
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#define CRC_16BIT_MASK 0x0000F0B8
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#define CRC_16BIT_PRES 0x0000FFFF
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#define DEFAULT_RFTHR 1
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#define DEFAULT_PPP_HEAD 0xff03
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#endif
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