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888be25402
If we are running BE8, the data and instruction endianness do not match, so use <asm/opcodes.h> to correctly translate memory accesses into ARM instructions. Acked-by: Jon Medhurst <tixy@linaro.org> Signed-off-by: Ben Dooks <ben.dooks@codethink.co.uk> [taras.kondratiuk@linaro.org: fixed Thumb instruction fetch order] Signed-off-by: Taras Kondratiuk <taras.kondratiuk@linaro.org>
172 lines
4.2 KiB
C
172 lines
4.2 KiB
C
/*
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* arch/arm/kernel/kprobes-common.c
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*
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* Copyright (C) 2011 Jon Medhurst <tixy@yxit.co.uk>.
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*
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* Some contents moved here from arch/arm/include/asm/kprobes-arm.c which is
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* Copyright (C) 2006, 2007 Motorola Inc.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#include <linux/kernel.h>
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#include <linux/kprobes.h>
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#include <asm/opcodes.h>
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#include "kprobes.h"
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static void __kprobes simulate_ldm1stm1(probes_opcode_t insn,
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struct arch_probes_insn *asi,
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struct pt_regs *regs)
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{
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int rn = (insn >> 16) & 0xf;
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int lbit = insn & (1 << 20);
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int wbit = insn & (1 << 21);
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int ubit = insn & (1 << 23);
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int pbit = insn & (1 << 24);
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long *addr = (long *)regs->uregs[rn];
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int reg_bit_vector;
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int reg_count;
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reg_count = 0;
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reg_bit_vector = insn & 0xffff;
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while (reg_bit_vector) {
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reg_bit_vector &= (reg_bit_vector - 1);
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++reg_count;
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}
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if (!ubit)
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addr -= reg_count;
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addr += (!pbit == !ubit);
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reg_bit_vector = insn & 0xffff;
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while (reg_bit_vector) {
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int reg = __ffs(reg_bit_vector);
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reg_bit_vector &= (reg_bit_vector - 1);
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if (lbit)
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regs->uregs[reg] = *addr++;
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else
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*addr++ = regs->uregs[reg];
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}
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if (wbit) {
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if (!ubit)
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addr -= reg_count;
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addr -= (!pbit == !ubit);
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regs->uregs[rn] = (long)addr;
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}
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}
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static void __kprobes simulate_stm1_pc(probes_opcode_t insn,
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struct arch_probes_insn *asi,
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struct pt_regs *regs)
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{
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unsigned long addr = regs->ARM_pc - 4;
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regs->ARM_pc = (long)addr + str_pc_offset;
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simulate_ldm1stm1(insn, asi, regs);
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regs->ARM_pc = (long)addr + 4;
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}
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static void __kprobes simulate_ldm1_pc(probes_opcode_t insn,
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struct arch_probes_insn *asi,
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struct pt_regs *regs)
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{
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simulate_ldm1stm1(insn, asi, regs);
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load_write_pc(regs->ARM_pc, regs);
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}
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static void __kprobes
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emulate_generic_r0_12_noflags(probes_opcode_t insn,
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struct arch_probes_insn *asi, struct pt_regs *regs)
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{
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register void *rregs asm("r1") = regs;
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register void *rfn asm("lr") = asi->insn_fn;
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__asm__ __volatile__ (
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"stmdb sp!, {%[regs], r11} \n\t"
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"ldmia %[regs], {r0-r12} \n\t"
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#if __LINUX_ARM_ARCH__ >= 6
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"blx %[fn] \n\t"
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#else
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"str %[fn], [sp, #-4]! \n\t"
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"adr lr, 1f \n\t"
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"ldr pc, [sp], #4 \n\t"
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"1: \n\t"
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#endif
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"ldr lr, [sp], #4 \n\t" /* lr = regs */
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"stmia lr, {r0-r12} \n\t"
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"ldr r11, [sp], #4 \n\t"
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: [regs] "=r" (rregs), [fn] "=r" (rfn)
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: "0" (rregs), "1" (rfn)
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: "r0", "r2", "r3", "r4", "r5", "r6", "r7",
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"r8", "r9", "r10", "r12", "memory", "cc"
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);
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}
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static void __kprobes
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emulate_generic_r2_14_noflags(probes_opcode_t insn,
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struct arch_probes_insn *asi, struct pt_regs *regs)
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{
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emulate_generic_r0_12_noflags(insn, asi,
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(struct pt_regs *)(regs->uregs+2));
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}
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static void __kprobes
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emulate_ldm_r3_15(probes_opcode_t insn,
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struct arch_probes_insn *asi, struct pt_regs *regs)
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{
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emulate_generic_r0_12_noflags(insn, asi,
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(struct pt_regs *)(regs->uregs+3));
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load_write_pc(regs->ARM_pc, regs);
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}
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enum probes_insn __kprobes
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kprobe_decode_ldmstm(probes_opcode_t insn, struct arch_probes_insn *asi,
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const struct decode_header *h)
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{
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probes_insn_handler_t *handler = 0;
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unsigned reglist = insn & 0xffff;
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int is_ldm = insn & 0x100000;
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int rn = (insn >> 16) & 0xf;
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if (rn <= 12 && (reglist & 0xe000) == 0) {
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/* Instruction only uses registers in the range R0..R12 */
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handler = emulate_generic_r0_12_noflags;
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} else if (rn >= 2 && (reglist & 0x8003) == 0) {
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/* Instruction only uses registers in the range R2..R14 */
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rn -= 2;
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reglist >>= 2;
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handler = emulate_generic_r2_14_noflags;
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} else if (rn >= 3 && (reglist & 0x0007) == 0) {
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/* Instruction only uses registers in the range R3..R15 */
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if (is_ldm && (reglist & 0x8000)) {
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rn -= 3;
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reglist >>= 3;
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handler = emulate_ldm_r3_15;
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}
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}
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if (handler) {
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/* We can emulate the instruction in (possibly) modified form */
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asi->insn[0] = __opcode_to_mem_arm((insn & 0xfff00000) |
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(rn << 16) | reglist);
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asi->insn_handler = handler;
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return INSN_GOOD;
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}
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/* Fallback to slower simulation... */
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if (reglist & 0x8000)
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handler = is_ldm ? simulate_ldm1_pc : simulate_stm1_pc;
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else
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handler = simulate_ldm1stm1;
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asi->insn_handler = handler;
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return INSN_GOOD_NO_SLOT;
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}
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