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40eb477678
The Generic Memory Interface bus can be used to connect high-speed devices such as NOR flash, FPGAs, DSPs... Signed-off-by: Mirza Krak <mirza.krak@gmail.com> Tested-by: Marcel Ziswiler <marcel.ziswiler@toradex.com> Tested-on: Colibri T20/T30 on EvalBoard V3.x and GMI-Memory Board Acked-by: Jon Hunter <jonathanh@nvidia.com> [treding@nvidia.com: symmetry and coding style OCD] Signed-off-by: Thierry Reding <treding@nvidia.com>
285 lines
7.5 KiB
C
285 lines
7.5 KiB
C
/*
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* Driver for NVIDIA Generic Memory Interface
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*
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* Copyright (C) 2016 Host Mobility AB. All rights reserved.
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*
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* This file is licensed under the terms of the GNU General Public
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* License version 2. This program is licensed "as is" without any
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* warranty of any kind, whether express or implied.
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*/
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#include <linux/clk.h>
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#include <linux/delay.h>
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#include <linux/io.h>
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#include <linux/module.h>
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#include <linux/of_device.h>
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#include <linux/reset.h>
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#define TEGRA_GMI_CONFIG 0x00
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#define TEGRA_GMI_CONFIG_GO BIT(31)
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#define TEGRA_GMI_BUS_WIDTH_32BIT BIT(30)
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#define TEGRA_GMI_MUX_MODE BIT(28)
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#define TEGRA_GMI_RDY_BEFORE_DATA BIT(24)
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#define TEGRA_GMI_RDY_ACTIVE_HIGH BIT(23)
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#define TEGRA_GMI_ADV_ACTIVE_HIGH BIT(22)
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#define TEGRA_GMI_OE_ACTIVE_HIGH BIT(21)
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#define TEGRA_GMI_CS_ACTIVE_HIGH BIT(20)
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#define TEGRA_GMI_CS_SELECT(x) ((x & 0x7) << 4)
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#define TEGRA_GMI_TIMING0 0x10
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#define TEGRA_GMI_MUXED_WIDTH(x) ((x & 0xf) << 12)
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#define TEGRA_GMI_HOLD_WIDTH(x) ((x & 0xf) << 8)
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#define TEGRA_GMI_ADV_WIDTH(x) ((x & 0xf) << 4)
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#define TEGRA_GMI_CE_WIDTH(x) (x & 0xf)
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#define TEGRA_GMI_TIMING1 0x14
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#define TEGRA_GMI_WE_WIDTH(x) ((x & 0xff) << 16)
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#define TEGRA_GMI_OE_WIDTH(x) ((x & 0xff) << 8)
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#define TEGRA_GMI_WAIT_WIDTH(x) (x & 0xff)
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#define TEGRA_GMI_MAX_CHIP_SELECT 8
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struct tegra_gmi {
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struct device *dev;
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void __iomem *base;
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struct clk *clk;
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struct reset_control *rst;
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u32 snor_config;
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u32 snor_timing0;
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u32 snor_timing1;
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};
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static int tegra_gmi_enable(struct tegra_gmi *gmi)
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{
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int err;
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err = clk_prepare_enable(gmi->clk);
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if (err < 0) {
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dev_err(gmi->dev, "failed to enable clock: %d\n", err);
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return err;
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}
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reset_control_assert(gmi->rst);
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usleep_range(2000, 4000);
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reset_control_deassert(gmi->rst);
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writel(gmi->snor_timing0, gmi->base + TEGRA_GMI_TIMING0);
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writel(gmi->snor_timing1, gmi->base + TEGRA_GMI_TIMING1);
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gmi->snor_config |= TEGRA_GMI_CONFIG_GO;
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writel(gmi->snor_config, gmi->base + TEGRA_GMI_CONFIG);
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return 0;
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}
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static void tegra_gmi_disable(struct tegra_gmi *gmi)
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{
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u32 config;
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/* stop GMI operation */
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config = readl(gmi->base + TEGRA_GMI_CONFIG);
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config &= ~TEGRA_GMI_CONFIG_GO;
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writel(config, gmi->base + TEGRA_GMI_CONFIG);
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reset_control_assert(gmi->rst);
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clk_disable_unprepare(gmi->clk);
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}
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static int tegra_gmi_parse_dt(struct tegra_gmi *gmi)
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{
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struct device_node *child;
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u32 property, ranges[4];
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int err;
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child = of_get_next_available_child(gmi->dev->of_node, NULL);
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if (!child) {
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dev_err(gmi->dev, "no child nodes found\n");
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return -ENODEV;
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}
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/*
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* We currently only support one child device due to lack of
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* chip-select address decoding. Which means that we only have one
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* chip-select line from the GMI controller.
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*/
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if (of_get_child_count(gmi->dev->of_node) > 1)
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dev_warn(gmi->dev, "only one child device is supported.");
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if (of_property_read_bool(child, "nvidia,snor-data-width-32bit"))
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gmi->snor_config |= TEGRA_GMI_BUS_WIDTH_32BIT;
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if (of_property_read_bool(child, "nvidia,snor-mux-mode"))
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gmi->snor_config |= TEGRA_GMI_MUX_MODE;
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if (of_property_read_bool(child, "nvidia,snor-rdy-active-before-data"))
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gmi->snor_config |= TEGRA_GMI_RDY_BEFORE_DATA;
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if (of_property_read_bool(child, "nvidia,snor-rdy-active-high"))
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gmi->snor_config |= TEGRA_GMI_RDY_ACTIVE_HIGH;
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if (of_property_read_bool(child, "nvidia,snor-adv-active-high"))
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gmi->snor_config |= TEGRA_GMI_ADV_ACTIVE_HIGH;
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if (of_property_read_bool(child, "nvidia,snor-oe-active-high"))
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gmi->snor_config |= TEGRA_GMI_OE_ACTIVE_HIGH;
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if (of_property_read_bool(child, "nvidia,snor-cs-active-high"))
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gmi->snor_config |= TEGRA_GMI_CS_ACTIVE_HIGH;
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/* Decode the CS# */
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err = of_property_read_u32_array(child, "ranges", ranges, 4);
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if (err < 0) {
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/* Invalid binding */
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if (err == -EOVERFLOW) {
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dev_err(gmi->dev,
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"failed to decode CS: invalid ranges length\n");
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goto error_cs;
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}
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/*
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* If we reach here it means that the child node has an empty
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* ranges or it does not exist at all. Attempt to decode the
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* CS# from the reg property instead.
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*/
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err = of_property_read_u32(child, "reg", &property);
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if (err < 0) {
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dev_err(gmi->dev,
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"failed to decode CS: no reg property found\n");
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goto error_cs;
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}
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} else {
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property = ranges[1];
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}
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/* Valid chip selects are CS0-CS7 */
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if (property >= TEGRA_GMI_MAX_CHIP_SELECT) {
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dev_err(gmi->dev, "invalid chip select: %d", property);
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err = -EINVAL;
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goto error_cs;
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}
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gmi->snor_config |= TEGRA_GMI_CS_SELECT(property);
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/* The default values that are provided below are reset values */
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if (!of_property_read_u32(child, "nvidia,snor-muxed-width", &property))
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gmi->snor_timing0 |= TEGRA_GMI_MUXED_WIDTH(property);
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else
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gmi->snor_timing0 |= TEGRA_GMI_MUXED_WIDTH(1);
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if (!of_property_read_u32(child, "nvidia,snor-hold-width", &property))
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gmi->snor_timing0 |= TEGRA_GMI_HOLD_WIDTH(property);
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else
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gmi->snor_timing0 |= TEGRA_GMI_HOLD_WIDTH(1);
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if (!of_property_read_u32(child, "nvidia,snor-adv-width", &property))
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gmi->snor_timing0 |= TEGRA_GMI_ADV_WIDTH(property);
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else
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gmi->snor_timing0 |= TEGRA_GMI_ADV_WIDTH(1);
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if (!of_property_read_u32(child, "nvidia,snor-ce-width", &property))
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gmi->snor_timing0 |= TEGRA_GMI_CE_WIDTH(property);
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else
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gmi->snor_timing0 |= TEGRA_GMI_CE_WIDTH(4);
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if (!of_property_read_u32(child, "nvidia,snor-we-width", &property))
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gmi->snor_timing1 |= TEGRA_GMI_WE_WIDTH(property);
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else
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gmi->snor_timing1 |= TEGRA_GMI_WE_WIDTH(1);
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if (!of_property_read_u32(child, "nvidia,snor-oe-width", &property))
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gmi->snor_timing1 |= TEGRA_GMI_OE_WIDTH(property);
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else
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gmi->snor_timing1 |= TEGRA_GMI_OE_WIDTH(1);
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if (!of_property_read_u32(child, "nvidia,snor-wait-width", &property))
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gmi->snor_timing1 |= TEGRA_GMI_WAIT_WIDTH(property);
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else
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gmi->snor_timing1 |= TEGRA_GMI_WAIT_WIDTH(3);
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error_cs:
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of_node_put(child);
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return err;
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}
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static int tegra_gmi_probe(struct platform_device *pdev)
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{
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struct device *dev = &pdev->dev;
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struct tegra_gmi *gmi;
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struct resource *res;
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int err;
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gmi = devm_kzalloc(dev, sizeof(*gmi), GFP_KERNEL);
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if (!gmi)
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return -ENOMEM;
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gmi->dev = dev;
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res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
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gmi->base = devm_ioremap_resource(dev, res);
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if (IS_ERR(gmi->base))
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return PTR_ERR(gmi->base);
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gmi->clk = devm_clk_get(dev, "gmi");
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if (IS_ERR(gmi->clk)) {
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dev_err(dev, "can not get clock\n");
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return PTR_ERR(gmi->clk);
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}
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gmi->rst = devm_reset_control_get(dev, "gmi");
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if (IS_ERR(gmi->rst)) {
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dev_err(dev, "can not get reset\n");
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return PTR_ERR(gmi->rst);
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}
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err = tegra_gmi_parse_dt(gmi);
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if (err)
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return err;
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err = tegra_gmi_enable(gmi);
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if (err < 0)
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return err;
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err = of_platform_default_populate(dev->of_node, NULL, dev);
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if (err < 0) {
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dev_err(dev, "fail to create devices.\n");
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tegra_gmi_disable(gmi);
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return err;
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}
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platform_set_drvdata(pdev, gmi);
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return 0;
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}
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static int tegra_gmi_remove(struct platform_device *pdev)
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{
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struct tegra_gmi *gmi = platform_get_drvdata(pdev);
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of_platform_depopulate(gmi->dev);
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tegra_gmi_disable(gmi);
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return 0;
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}
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static const struct of_device_id tegra_gmi_id_table[] = {
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{ .compatible = "nvidia,tegra20-gmi", },
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{ .compatible = "nvidia,tegra30-gmi", },
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{ }
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};
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MODULE_DEVICE_TABLE(of, tegra_gmi_id_table);
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static struct platform_driver tegra_gmi_driver = {
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.probe = tegra_gmi_probe,
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.remove = tegra_gmi_remove,
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.driver = {
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.name = "tegra-gmi",
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.of_match_table = tegra_gmi_id_table,
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},
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};
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module_platform_driver(tegra_gmi_driver);
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MODULE_AUTHOR("Mirza Krak <mirza.krak@gmail.com");
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MODULE_DESCRIPTION("NVIDIA Tegra GMI Bus Driver");
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MODULE_LICENSE("GPL v2");
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