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3c1763115b
Adding 'S' event/group modifier to specify that the event value/s are
read by PERF_SAMPLE_READ sample type processing, instead of the period
value offered by lower layers.
There's additional behaviour change for 'S' modifier being specified on
event group:
Currently all the events within a group makes samples. If user now
specifies 'S' within group modifier, only the leader will trigger
samples. The rest of events in the group will have sampling disabled.
And same as for single events, values of all events within the group
(including leader) are read by PERF_SAMPLE_READ sample type processing.
Following example will create event group with cycles and cache-misses
events, setting the cycles as group leader and the only event to
actually sample. Both cycles and cache-misses event period values are
read by PERF_SAMPLE_READ sample type processing with PERF_FORMAT_GROUP
read format.
Example:
$ perf record -e '{cycles,cache-misses}:S' ls
...
$ perf report --group --show-total-period --stdio
...
# Samples: 36 of event 'anon group { cycles, cache-misses }'
# Event count (approx.): 12585593
#
# Overhead Period Command Shared Object Symbol
# .............. .............. ....... ................. ..........................
#
19.92% 1.20% 2505936 31 ls [kernel.kallsyms] [k] mark_held_locks
13.74% 0.47% 1729327 12 ls [kernel.kallsyms] [k] sched_clock_local
13.64% 23.72% 1716147 612 ls ld-2.14.90.so [.] check_match.10805
13.12% 23.22% 1650778 599 ls libc-2.14.90.so [.] _nl_intern_locale_data
11.24% 29.19% 1414554 753 ls [kernel.kallsyms] [k] sched_clock_cpu
8.50% 0.35% 1070150 9 ls [kernel.kallsyms] [k] check_chain_key
...
Signed-off-by: Jiri Olsa <jolsa@redhat.com>
Acked-by: Namhyung Kim <namhyung@kernel.org>
Cc: Corey Ashford <cjashfor@linux.vnet.ibm.com>
Cc: Frederic Weisbecker <fweisbec@gmail.com>
Cc: Namhyung Kim <namhyung@kernel.org>
Cc: Paul Mackerras <paulus@samba.org>
Cc: Peter Zijlstra <a.p.zijlstra@chello.nl>
Link: http://lkml.kernel.org/n/tip-iyoinu3axi11mymwnh2b7fxj@git.kernel.org
Signed-off-by: Arnaldo Carvalho de Melo <acme@redhat.com>
122 lines
4.3 KiB
Plaintext
122 lines
4.3 KiB
Plaintext
perf-list(1)
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============
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NAME
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----
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perf-list - List all symbolic event types
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SYNOPSIS
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--------
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[verse]
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'perf list' [hw|sw|cache|tracepoint|pmu|event_glob]
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DESCRIPTION
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-----------
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This command displays the symbolic event types which can be selected in the
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various perf commands with the -e option.
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[[EVENT_MODIFIERS]]
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EVENT MODIFIERS
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---------------
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Events can optionally have a modifer by appending a colon and one or
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more modifiers. Modifiers allow the user to restrict the events to be
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counted. The following modifiers exist:
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u - user-space counting
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k - kernel counting
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h - hypervisor counting
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G - guest counting (in KVM guests)
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H - host counting (not in KVM guests)
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p - precise level
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S - read sample value (PERF_SAMPLE_READ)
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The 'p' modifier can be used for specifying how precise the instruction
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address should be. The 'p' modifier can be specified multiple times:
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0 - SAMPLE_IP can have arbitrary skid
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1 - SAMPLE_IP must have constant skid
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2 - SAMPLE_IP requested to have 0 skid
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3 - SAMPLE_IP must have 0 skid
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For Intel systems precise event sampling is implemented with PEBS
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which supports up to precise-level 2.
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On AMD systems it is implemented using IBS (up to precise-level 2).
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The precise modifier works with event types 0x76 (cpu-cycles, CPU
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clocks not halted) and 0xC1 (micro-ops retired). Both events map to
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IBS execution sampling (IBS op) with the IBS Op Counter Control bit
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(IbsOpCntCtl) set respectively (see AMD64 Architecture Programmer’s
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Manual Volume 2: System Programming, 13.3 Instruction-Based
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Sampling). Examples to use IBS:
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perf record -a -e cpu-cycles:p ... # use ibs op counting cycles
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perf record -a -e r076:p ... # same as -e cpu-cycles:p
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perf record -a -e r0C1:p ... # use ibs op counting micro-ops
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RAW HARDWARE EVENT DESCRIPTOR
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-----------------------------
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Even when an event is not available in a symbolic form within perf right now,
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it can be encoded in a per processor specific way.
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For instance For x86 CPUs NNN represents the raw register encoding with the
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layout of IA32_PERFEVTSELx MSRs (see [Intel® 64 and IA-32 Architectures Software Developer's Manual Volume 3B: System Programming Guide] Figure 30-1 Layout
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of IA32_PERFEVTSELx MSRs) or AMD's PerfEvtSeln (see [AMD64 Architecture Programmer’s Manual Volume 2: System Programming], Page 344,
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Figure 13-7 Performance Event-Select Register (PerfEvtSeln)).
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Note: Only the following bit fields can be set in x86 counter
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registers: event, umask, edge, inv, cmask. Esp. guest/host only and
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OS/user mode flags must be setup using <<EVENT_MODIFIERS, EVENT
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MODIFIERS>>.
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Example:
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If the Intel docs for a QM720 Core i7 describe an event as:
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Event Umask Event Mask
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Num. Value Mnemonic Description Comment
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A8H 01H LSD.UOPS Counts the number of micro-ops Use cmask=1 and
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delivered by loop stream detector invert to count
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cycles
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raw encoding of 0x1A8 can be used:
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perf stat -e r1a8 -a sleep 1
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perf record -e r1a8 ...
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You should refer to the processor specific documentation for getting these
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details. Some of them are referenced in the SEE ALSO section below.
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OPTIONS
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-------
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Without options all known events will be listed.
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To limit the list use:
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. 'hw' or 'hardware' to list hardware events such as cache-misses, etc.
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. 'sw' or 'software' to list software events such as context switches, etc.
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. 'cache' or 'hwcache' to list hardware cache events such as L1-dcache-loads, etc.
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. 'tracepoint' to list all tracepoint events, alternatively use
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'subsys_glob:event_glob' to filter by tracepoint subsystems such as sched,
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block, etc.
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. 'pmu' to print the kernel supplied PMU events.
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. If none of the above is matched, it will apply the supplied glob to all
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events, printing the ones that match.
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One or more types can be used at the same time, listing the events for the
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types specified.
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SEE ALSO
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--------
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linkperf:perf-stat[1], linkperf:perf-top[1],
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linkperf:perf-record[1],
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http://www.intel.com/Assets/PDF/manual/253669.pdf[Intel® 64 and IA-32 Architectures Software Developer's Manual Volume 3B: System Programming Guide],
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http://support.amd.com/us/Processor_TechDocs/24593_APM_v2.pdf[AMD64 Architecture Programmer’s Manual Volume 2: System Programming]
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