mirror of
https://github.com/edk2-porting/linux-next.git
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3c101c41fb
These changes fix some of the more meaningful warnings that smatch returns for the OMAP subarch code, and unwraps strings that are wrapped at the 80-column boundary, to conform with the current practice. Basic build, boot, and PM logs are available here: http://www.pwsan.com/omap/testlogs/warnings_a_cleanup_3.7/20120912025927/ -----BEGIN PGP SIGNATURE----- Version: GnuPG v1.4.12 (GNU/Linux) iQIcBAABAgAGBQJQUKL1AAoJEMePsQ0LvSpL+a8QAJlJR9uwqUKu60GfbQEeegce k6pr0xXYvHEmbro/v6O4ezs2o716EBgwBWnId97oOZvVnwhPbEHR87UH8FFOIWOQ +/ui5MxXtYWNjYcDOzdF95reFM1szAAxQu8k9wXg+WBtZ4zCkhknpoftShRbOdg0 BgO0r1iY/wuoFaYgGFKSNdObPVgSTENjbtg/LVvB/V3PQjYmUBosJVH0tPO/LQio pWhozfFuiWbARYxPg6dMOn8yQ5mCeWErpv4WZjM+dgcrkLYyPdI2uUS3Ka8F7Az2 ImC+k0gU6WwkjyKqv/SG2wg5+3Sh8ZZsX0EKXwq0gQEmLWacENS1ELRT3+HcxGru HoAhE46URb4NGzBt7rkIkGg0HcajfORDtZSrGfsEclDmrVV5+JgUzC+PEDiwSxVU LqpJIZ8lxjqBNPSlmXqtEgTG32M6E9fDII8JdGC64vUv+vXzuhpJCXF78I8+A+Hv oSBbTOCzYGz1xp06G6Hzadpo5I1LocBRemsnhw2O9oNDdUZxiGo/qJcWfk2wpMQ6 4c/kHbYEsJ6/7eVe5kNtdkeptAXp1AFO5XIhQpSAs1O1Rr++nDNahaUJA56xev8x GoEZCYLGMGpQnINW6g0Srzwp8n1ywSgt3Gt2fbDTAP+Q02DPT3IIWWs4LlIDIrjZ w0q1kAp1+In5is3pxJvT =ythb -----END PGP SIGNATURE----- Merge tag 'omap-cleanup-b-for-3.7' of git://git.kernel.org/pub/scm/linux/kernel/git/pjw/omap-pending into cleanup-makefile-sparse smatch and string-wrapping cleanups for the OMAP subarch code. These changes fix some of the more meaningful warnings that smatch returns for the OMAP subarch code, and unwraps strings that are wrapped at the 80-column boundary, to conform with the current practice. Basic build, boot, and PM logs are available here: http://www.pwsan.com/omap/testlogs/warnings_a_cleanup_3.7/20120912025927/
394 lines
8.5 KiB
C
394 lines
8.5 KiB
C
/*
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* OMAP1/OMAP7xx - specific DMA driver
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*
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* Copyright (C) 2003 - 2008 Nokia Corporation
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* Author: Juha Yrjölä <juha.yrjola@nokia.com>
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* DMA channel linking for 1610 by Samuel Ortiz <samuel.ortiz@nokia.com>
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* Graphics DMA and LCD DMA graphics tranformations
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* by Imre Deak <imre.deak@nokia.com>
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* OMAP2/3 support Copyright (C) 2004-2007 Texas Instruments, Inc.
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* Some functions based on earlier dma-omap.c Copyright (C) 2001 RidgeRun, Inc.
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*
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* Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/
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* Converted DMA library into platform driver
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* - G, Manjunath Kondaiah <manjugk@ti.com>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#include <linux/err.h>
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#include <linux/slab.h>
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#include <linux/module.h>
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#include <linux/init.h>
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#include <linux/device.h>
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#include <linux/io.h>
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#include <plat/dma.h>
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#include <plat/tc.h>
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#include <mach/irqs.h>
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#define OMAP1_DMA_BASE (0xfffed800)
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#define OMAP1_LOGICAL_DMA_CH_COUNT 17
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#define OMAP1_DMA_STRIDE 0x40
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static u32 errata;
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static u32 enable_1510_mode;
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static u8 dma_stride;
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static enum omap_reg_offsets dma_common_ch_start, dma_common_ch_end;
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static u16 reg_map[] = {
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[GCR] = 0x400,
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[GSCR] = 0x404,
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[GRST1] = 0x408,
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[HW_ID] = 0x442,
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[PCH2_ID] = 0x444,
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[PCH0_ID] = 0x446,
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[PCH1_ID] = 0x448,
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[PCHG_ID] = 0x44a,
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[PCHD_ID] = 0x44c,
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[CAPS_0] = 0x44e,
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[CAPS_1] = 0x452,
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[CAPS_2] = 0x456,
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[CAPS_3] = 0x458,
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[CAPS_4] = 0x45a,
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[PCH2_SR] = 0x460,
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[PCH0_SR] = 0x480,
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[PCH1_SR] = 0x482,
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[PCHD_SR] = 0x4c0,
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/* Common Registers */
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[CSDP] = 0x00,
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[CCR] = 0x02,
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[CICR] = 0x04,
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[CSR] = 0x06,
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[CEN] = 0x10,
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[CFN] = 0x12,
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[CSFI] = 0x14,
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[CSEI] = 0x16,
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[CPC] = 0x18, /* 15xx only */
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[CSAC] = 0x18,
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[CDAC] = 0x1a,
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[CDEI] = 0x1c,
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[CDFI] = 0x1e,
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[CLNK_CTRL] = 0x28,
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/* Channel specific register offsets */
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[CSSA] = 0x08,
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[CDSA] = 0x0c,
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[COLOR] = 0x20,
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[CCR2] = 0x24,
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[LCH_CTRL] = 0x2a,
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};
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static struct resource res[] __initdata = {
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[0] = {
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.start = OMAP1_DMA_BASE,
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.end = OMAP1_DMA_BASE + SZ_2K - 1,
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.flags = IORESOURCE_MEM,
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},
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[1] = {
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.name = "0",
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.start = INT_DMA_CH0_6,
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.flags = IORESOURCE_IRQ,
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},
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[2] = {
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.name = "1",
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.start = INT_DMA_CH1_7,
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.flags = IORESOURCE_IRQ,
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},
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[3] = {
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.name = "2",
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.start = INT_DMA_CH2_8,
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.flags = IORESOURCE_IRQ,
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},
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[4] = {
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.name = "3",
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.start = INT_DMA_CH3,
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.flags = IORESOURCE_IRQ,
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},
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[5] = {
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.name = "4",
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.start = INT_DMA_CH4,
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.flags = IORESOURCE_IRQ,
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},
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[6] = {
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.name = "5",
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.start = INT_DMA_CH5,
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.flags = IORESOURCE_IRQ,
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},
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/* Handled in lcd_dma.c */
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[7] = {
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.name = "6",
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.start = INT_1610_DMA_CH6,
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.flags = IORESOURCE_IRQ,
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},
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/* irq's for omap16xx and omap7xx */
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[8] = {
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.name = "7",
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.start = INT_1610_DMA_CH7,
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.flags = IORESOURCE_IRQ,
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},
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[9] = {
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.name = "8",
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.start = INT_1610_DMA_CH8,
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.flags = IORESOURCE_IRQ,
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},
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[10] = {
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.name = "9",
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.start = INT_1610_DMA_CH9,
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.flags = IORESOURCE_IRQ,
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},
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[11] = {
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.name = "10",
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.start = INT_1610_DMA_CH10,
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.flags = IORESOURCE_IRQ,
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},
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[12] = {
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.name = "11",
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.start = INT_1610_DMA_CH11,
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.flags = IORESOURCE_IRQ,
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},
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[13] = {
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.name = "12",
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.start = INT_1610_DMA_CH12,
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.flags = IORESOURCE_IRQ,
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},
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[14] = {
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.name = "13",
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.start = INT_1610_DMA_CH13,
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.flags = IORESOURCE_IRQ,
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},
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[15] = {
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.name = "14",
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.start = INT_1610_DMA_CH14,
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.flags = IORESOURCE_IRQ,
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},
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[16] = {
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.name = "15",
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.start = INT_1610_DMA_CH15,
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.flags = IORESOURCE_IRQ,
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},
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[17] = {
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.name = "16",
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.start = INT_DMA_LCD,
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.flags = IORESOURCE_IRQ,
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},
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};
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static void __iomem *dma_base;
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static inline void dma_write(u32 val, int reg, int lch)
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{
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u8 stride;
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u32 offset;
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stride = (reg >= dma_common_ch_start) ? dma_stride : 0;
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offset = reg_map[reg] + (stride * lch);
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__raw_writew(val, dma_base + offset);
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if ((reg > CLNK_CTRL && reg < CCEN) ||
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(reg > PCHD_ID && reg < CAPS_2)) {
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u32 offset2 = reg_map[reg] + 2 + (stride * lch);
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__raw_writew(val >> 16, dma_base + offset2);
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}
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}
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static inline u32 dma_read(int reg, int lch)
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{
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u8 stride;
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u32 offset, val;
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stride = (reg >= dma_common_ch_start) ? dma_stride : 0;
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offset = reg_map[reg] + (stride * lch);
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val = __raw_readw(dma_base + offset);
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if ((reg > CLNK_CTRL && reg < CCEN) ||
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(reg > PCHD_ID && reg < CAPS_2)) {
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u16 upper;
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u32 offset2 = reg_map[reg] + 2 + (stride * lch);
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upper = __raw_readw(dma_base + offset2);
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val |= (upper << 16);
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}
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return val;
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}
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static void omap1_clear_lch_regs(int lch)
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{
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int i = dma_common_ch_start;
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for (; i <= dma_common_ch_end; i += 1)
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dma_write(0, i, lch);
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}
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static void omap1_clear_dma(int lch)
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{
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u32 l;
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l = dma_read(CCR, lch);
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l &= ~OMAP_DMA_CCR_EN;
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dma_write(l, CCR, lch);
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/* Clear pending interrupts */
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l = dma_read(CSR, lch);
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}
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static void omap1_show_dma_caps(void)
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{
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if (enable_1510_mode) {
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printk(KERN_INFO "DMA support for OMAP15xx initialized\n");
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} else {
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u16 w;
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printk(KERN_INFO "OMAP DMA hardware version %d\n",
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dma_read(HW_ID, 0));
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printk(KERN_INFO "DMA capabilities: %08x:%08x:%04x:%04x:%04x\n",
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dma_read(CAPS_0, 0), dma_read(CAPS_1, 0),
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dma_read(CAPS_2, 0), dma_read(CAPS_3, 0),
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dma_read(CAPS_4, 0));
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/* Disable OMAP 3.0/3.1 compatibility mode. */
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w = dma_read(GSCR, 0);
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w |= 1 << 3;
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dma_write(w, GSCR, 0);
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}
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return;
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}
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static u32 configure_dma_errata(void)
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{
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/*
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* Erratum 3.2/3.3: sometimes 0 is returned if CSAC/CDAC is
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* read before the DMA controller finished disabling the channel.
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*/
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if (!cpu_is_omap15xx())
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SET_DMA_ERRATA(DMA_ERRATA_3_3);
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return errata;
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}
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static int __init omap1_system_dma_init(void)
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{
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struct omap_system_dma_plat_info *p;
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struct omap_dma_dev_attr *d;
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struct platform_device *pdev;
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int ret;
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pdev = platform_device_alloc("omap_dma_system", 0);
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if (!pdev) {
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pr_err("%s: Unable to device alloc for dma\n",
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__func__);
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return -ENOMEM;
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}
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dma_base = ioremap(res[0].start, resource_size(&res[0]));
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if (!dma_base) {
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pr_err("%s: Unable to ioremap\n", __func__);
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ret = -ENODEV;
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goto exit_device_put;
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}
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ret = platform_device_add_resources(pdev, res, ARRAY_SIZE(res));
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if (ret) {
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dev_err(&pdev->dev, "%s: Unable to add resources for %s%d\n",
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__func__, pdev->name, pdev->id);
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goto exit_device_put;
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}
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p = kzalloc(sizeof(struct omap_system_dma_plat_info), GFP_KERNEL);
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if (!p) {
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dev_err(&pdev->dev, "%s: Unable to allocate 'p' for %s\n",
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__func__, pdev->name);
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ret = -ENOMEM;
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goto exit_device_del;
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}
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d = kzalloc(sizeof(struct omap_dma_dev_attr), GFP_KERNEL);
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if (!d) {
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dev_err(&pdev->dev, "%s: Unable to allocate 'd' for %s\n",
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__func__, pdev->name);
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ret = -ENOMEM;
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goto exit_release_p;
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}
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d->lch_count = OMAP1_LOGICAL_DMA_CH_COUNT;
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/* Valid attributes for omap1 plus processors */
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if (cpu_is_omap15xx())
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d->dev_caps = ENABLE_1510_MODE;
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enable_1510_mode = d->dev_caps & ENABLE_1510_MODE;
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d->dev_caps |= SRC_PORT;
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d->dev_caps |= DST_PORT;
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d->dev_caps |= SRC_INDEX;
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d->dev_caps |= DST_INDEX;
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d->dev_caps |= IS_BURST_ONLY4;
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d->dev_caps |= CLEAR_CSR_ON_READ;
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d->dev_caps |= IS_WORD_16;
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d->chan = kzalloc(sizeof(struct omap_dma_lch) *
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(d->lch_count), GFP_KERNEL);
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if (!d->chan) {
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dev_err(&pdev->dev,
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"%s: Memory allocation failed for d->chan!\n",
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__func__);
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goto exit_release_d;
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}
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if (cpu_is_omap15xx())
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d->chan_count = 9;
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else if (cpu_is_omap16xx() || cpu_is_omap7xx()) {
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if (!(d->dev_caps & ENABLE_1510_MODE))
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d->chan_count = 16;
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else
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d->chan_count = 9;
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}
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p->dma_attr = d;
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p->show_dma_caps = omap1_show_dma_caps;
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p->clear_lch_regs = omap1_clear_lch_regs;
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p->clear_dma = omap1_clear_dma;
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p->dma_write = dma_write;
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p->dma_read = dma_read;
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p->disable_irq_lch = NULL;
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p->errata = configure_dma_errata();
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ret = platform_device_add_data(pdev, p, sizeof(*p));
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if (ret) {
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dev_err(&pdev->dev, "%s: Unable to add resources for %s%d\n",
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__func__, pdev->name, pdev->id);
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goto exit_release_chan;
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}
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ret = platform_device_add(pdev);
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if (ret) {
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dev_err(&pdev->dev, "%s: Unable to add resources for %s%d\n",
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__func__, pdev->name, pdev->id);
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goto exit_release_chan;
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}
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dma_stride = OMAP1_DMA_STRIDE;
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dma_common_ch_start = CPC;
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dma_common_ch_end = COLOR;
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return ret;
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exit_release_chan:
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kfree(d->chan);
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exit_release_d:
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kfree(d);
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exit_release_p:
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kfree(p);
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exit_device_del:
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platform_device_del(pdev);
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exit_device_put:
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platform_device_put(pdev);
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return ret;
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}
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arch_initcall(omap1_system_dma_init);
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