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https://github.com/edk2-porting/linux-next.git
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55ba99eb21
This adds preliminary support for the SH7786 CPU subtype. While this is a dual-core CPU, only UP is supported for now. L2 cache support is likewise not yet implemented. More information on this particular CPU subtype is available at: http://www.renesas.com/fmwk.jsp?cnt=sh7786_root.jsp&fp=/products/mpumcu/superh_family/sh7780_series/sh7786_group/ Signed-off-by: Kuninori Morimoto <morimoto.kuninori@renesas.com> Signed-off-by: Paul Mundt <lethal@linux-sh.org>
193 lines
3.6 KiB
C
193 lines
3.6 KiB
C
/*
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* SH7786 Pinmux
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*
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* Copyright (C) 2008, 2009 Renesas Solutions Corp.
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* Kuninori Morimoto <morimoto.kuninori@renesas.com>
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*
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* Based on sh7785.h
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*
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* This file is subject to the terms and conditions of the GNU General Public
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* License. See the file "COPYING" in the main directory of this archive
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* for more details.
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*/
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#ifndef __CPU_SH7786_H__
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#define __CPU_SH7786_H__
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enum {
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/* PA */
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GPIO_PA7, GPIO_PA6, GPIO_PA5, GPIO_PA4,
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GPIO_PA3, GPIO_PA2, GPIO_PA1, GPIO_PA0,
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/* PB */
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GPIO_PB7, GPIO_PB6, GPIO_PB5, GPIO_PB4,
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GPIO_PB3, GPIO_PB2, GPIO_PB1, GPIO_PB0,
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/* PC */
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GPIO_PC7, GPIO_PC6, GPIO_PC5, GPIO_PC4,
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GPIO_PC3, GPIO_PC2, GPIO_PC1, GPIO_PC0,
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/* PD */
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GPIO_PD7, GPIO_PD6, GPIO_PD5, GPIO_PD4,
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GPIO_PD3, GPIO_PD2, GPIO_PD1, GPIO_PD0,
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/* PE */
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GPIO_PE5, GPIO_PE4, GPIO_PE3, GPIO_PE2,
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GPIO_PE1, GPIO_PE0,
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/* PF */
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GPIO_PF7, GPIO_PF6, GPIO_PF5, GPIO_PF4,
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GPIO_PF3, GPIO_PF2, GPIO_PF1, GPIO_PF0,
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/* PG */
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GPIO_PG7, GPIO_PG6, GPIO_PG5, GPIO_PG4,
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GPIO_PG3, GPIO_PG2, GPIO_PG1, GPIO_PG0,
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/* PH */
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GPIO_PH7, GPIO_PH6, GPIO_PH5, GPIO_PH4,
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GPIO_PH3, GPIO_PH2, GPIO_PH1, GPIO_PH0,
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/* PJ */
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GPIO_PJ7, GPIO_PJ6, GPIO_PJ5, GPIO_PJ4,
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GPIO_PJ3, GPIO_PJ2, GPIO_PJ1, GPIO_PJ0,
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GPIO_FN_CDE,
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GPIO_FN_ETH_MAGIC,
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GPIO_FN_DISP,
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GPIO_FN_ETH_LINK,
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GPIO_FN_DR5,
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GPIO_FN_ETH_TX_ER,
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GPIO_FN_DR4,
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GPIO_FN_ETH_TX_EN,
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GPIO_FN_DR3,
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GPIO_FN_ETH_TXD3,
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GPIO_FN_DR2,
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GPIO_FN_ETH_TXD2,
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GPIO_FN_DR1,
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GPIO_FN_ETH_TXD1,
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GPIO_FN_DR0,
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GPIO_FN_ETH_TXD0,
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GPIO_FN_VSYNC,
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GPIO_FN_HSPI_CLK,
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GPIO_FN_ODDF,
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GPIO_FN_HSPI_CS,
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GPIO_FN_DG5,
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GPIO_FN_ETH_MDIO,
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GPIO_FN_DG4,
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GPIO_FN_ETH_RX_CLK,
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GPIO_FN_DG3,
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GPIO_FN_ETH_MDC,
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GPIO_FN_DG2,
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GPIO_FN_ETH_COL,
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GPIO_FN_DG1,
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GPIO_FN_ETH_TX_CLK,
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GPIO_FN_DG0,
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GPIO_FN_ETH_CRS,
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GPIO_FN_DCLKIN,
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GPIO_FN_HSPI_RX,
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GPIO_FN_HSYNC,
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GPIO_FN_HSPI_TX,
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GPIO_FN_DB5,
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GPIO_FN_ETH_RXD3,
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GPIO_FN_DB4,
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GPIO_FN_ETH_RXD2,
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GPIO_FN_DB3,
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GPIO_FN_ETH_RXD1,
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GPIO_FN_DB2,
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GPIO_FN_ETH_RXD0,
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GPIO_FN_DB1,
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GPIO_FN_ETH_RX_DV,
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GPIO_FN_DB0,
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GPIO_FN_ETH_RX_ER,
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GPIO_FN_DCLKOUT,
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GPIO_FN_SCIF1_SLK,
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GPIO_FN_SCIF1_RXD,
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GPIO_FN_SCIF1_TXD,
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GPIO_FN_DACK1,
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GPIO_FN_BACK,
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GPIO_FN_FALE,
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GPIO_FN_DACK0,
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GPIO_FN_FCLE,
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GPIO_FN_DREQ1,
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GPIO_FN_BREQ,
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GPIO_FN_USB_OVC1,
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GPIO_FN_DREQ0,
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GPIO_FN_USB_OVC0,
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GPIO_FN_USB_PENC1,
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GPIO_FN_USB_PENC0,
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GPIO_FN_HAC1_SDOUT,
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GPIO_FN_SSI1_SDATA,
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GPIO_FN_SDIF1CMD,
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GPIO_FN_HAC1_SDIN,
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GPIO_FN_SSI1_SCK,
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GPIO_FN_SDIF1CD,
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GPIO_FN_HAC1_SYNC,
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GPIO_FN_SSI1_WS,
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GPIO_FN_SDIF1WP,
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GPIO_FN_HAC1_BITCLK,
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GPIO_FN_SSI1_CLK,
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GPIO_FN_SDIF1CLK,
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GPIO_FN_HAC0_SDOUT,
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GPIO_FN_SSI0_SDATA,
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GPIO_FN_SDIF1D3,
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GPIO_FN_HAC0_SDIN,
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GPIO_FN_SSI0_SCK,
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GPIO_FN_SDIF1D2,
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GPIO_FN_HAC0_SYNC,
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GPIO_FN_SSI0_WS,
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GPIO_FN_SDIF1D1,
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GPIO_FN_HAC0_BITCLK,
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GPIO_FN_SSI0_CLK,
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GPIO_FN_SDIF1D0,
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GPIO_FN_SCIF3_SCK,
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GPIO_FN_SSI2_SDATA,
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GPIO_FN_SCIF3_RXD,
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GPIO_FN_TCLK,
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GPIO_FN_SSI2_SCK,
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GPIO_FN_SCIF3_TXD,
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GPIO_FN_HAC_RES,
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GPIO_FN_SSI2_WS,
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GPIO_FN_DACK3,
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GPIO_FN_SDIF0CMD,
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GPIO_FN_DACK2,
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GPIO_FN_SDIF0CD,
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GPIO_FN_DREQ3,
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GPIO_FN_SDIF0WP,
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GPIO_FN_SCIF0_CTS,
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GPIO_FN_DREQ2,
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GPIO_FN_SDIF0CLK,
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GPIO_FN_SCIF0_RTS,
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GPIO_FN_IRL7,
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GPIO_FN_SDIF0D3,
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GPIO_FN_SCIF0_SCK,
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GPIO_FN_IRL6,
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GPIO_FN_SDIF0D2,
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GPIO_FN_SCIF0_RXD,
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GPIO_FN_IRL5,
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GPIO_FN_SDIF0D1,
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GPIO_FN_SCIF0_TXD,
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GPIO_FN_IRL4,
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GPIO_FN_SDIF0D0,
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GPIO_FN_SCIF5_SCK,
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GPIO_FN_FRB,
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GPIO_FN_SCIF5_RXD,
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GPIO_FN_IOIS16,
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GPIO_FN_SCIF5_TXD,
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GPIO_FN_CE2B,
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GPIO_FN_DRAK3,
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GPIO_FN_CE2A,
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GPIO_FN_SCIF4_SCK,
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GPIO_FN_DRAK2,
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GPIO_FN_SSI3_WS,
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GPIO_FN_SCIF4_RXD,
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GPIO_FN_DRAK1,
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GPIO_FN_SSI3_SDATA,
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GPIO_FN_FSTATUS,
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GPIO_FN_SCIF4_TXD,
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GPIO_FN_DRAK0,
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GPIO_FN_SSI3_SCK,
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GPIO_FN_FSE,
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};
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#endif /* __CPU_SH7786_H__ */
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