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b9d4d42ad9
This patch removes the __ARCH_WANT_INTERRUPTS_ON_CTXSW definition for ARMv5 and earlier processors. On such processors, the context switch requires a full cache flush. To avoid high interrupt latencies, this patch defers the mm switching to the post-lock switch hook if the interrupts are disabled. Reviewed-by: Will Deacon <will.deacon@arm.com> Tested-by: Will Deacon <will.deacon@arm.com> Reviewed-by: Frank Rowand <frank.rowand@am.sony.com> Tested-by: Marc Zyngier <Marc.Zyngier@arm.com> Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
38 lines
732 B
C
38 lines
732 B
C
#ifndef __ARM_MMU_H
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#define __ARM_MMU_H
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#ifdef CONFIG_MMU
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typedef struct {
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#ifdef CONFIG_CPU_HAS_ASID
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unsigned int id;
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raw_spinlock_t id_lock;
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#endif
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unsigned int kvm_seq;
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} mm_context_t;
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#ifdef CONFIG_CPU_HAS_ASID
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#define ASID(mm) ((mm)->context.id & 255)
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/* init_mm.context.id_lock should be initialized. */
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#define INIT_MM_CONTEXT(name) \
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.context.id_lock = __RAW_SPIN_LOCK_UNLOCKED(name.context.id_lock),
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#else
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#define ASID(mm) (0)
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#endif
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#else
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/*
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* From nommu.h:
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* Copyright (C) 2002, David McCullough <davidm@snapgear.com>
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* modified for 2.6 by Hyok S. Choi <hyok.choi@samsung.com>
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*/
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typedef struct {
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unsigned long end_brk;
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} mm_context_t;
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#endif
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#endif
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