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db0d4db22a
The GIC support code is heavily using the fact that hardware implementations are exposing banked registers. Unfortunately, it looks like at least one GIC implementation (EXYNOS) offers both the distributor and the CPU interfaces at different addresses, depending on the CPU. This problem is solved by allowing the distributor and CPU interface addresses to be per-cpu variables for the platforms that require it. The EXYNOS code is updated not to mess with the GIC internals while handling interrupts, and struct gic_chip_data is back to being private. The DT binding for the gic is updated to allow an optional "cpu-offset" value, which is used to compute the various base addresses. Finally, a new config option (GIC_NON_BANKED) is used to control this feature, so the overhead is only present on kernels compiled with support for EXYNOS. Tested on Origen (EXYNOS4) and Panda (OMAP4). Cc: Kukjin Kim <kgene.kim@samsung.com> Cc: Will Deacon <will.deacon@arm.com> Cc: Thomas Abraham <thomas.abraham@linaro.org> Acked-by: Rob Herring <rob.herring@calxeda.com> Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
127 lines
2.6 KiB
Plaintext
127 lines
2.6 KiB
Plaintext
# arch/arm/plat-s5p/Kconfig
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#
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# Copyright (c) 2009 Samsung Electronics Co., Ltd.
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# http://www.samsung.com/
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#
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# Licensed under GPLv2
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config PLAT_S5P
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bool
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depends on (ARCH_S5P64X0 || ARCH_S5PC100 || ARCH_S5PV210 || ARCH_EXYNOS)
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default y
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select ARM_VIC if !ARCH_EXYNOS4
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select ARM_GIC if ARCH_EXYNOS4
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select GIC_NON_BANKED if ARCH_EXYNOS4
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select NO_IOPORT
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select ARCH_REQUIRE_GPIOLIB
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select S3C_GPIO_TRACK
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select S5P_GPIO_DRVSTR
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select SAMSUNG_GPIOLIB_4BIT
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select PLAT_SAMSUNG
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select SAMSUNG_CLKSRC
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select SAMSUNG_IRQ_VIC_TIMER
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help
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Base platform code for Samsung's S5P series SoC.
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config S5P_EXT_INT
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bool
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help
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Use the external interrupts (other than GPIO interrupts.)
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Note: Do not choose this for S5P6440 and S5P6450.
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config S5P_GPIO_INT
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bool
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help
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Common code for the GPIO interrupts (other than external interrupts.)
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config S5P_HRT
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bool
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select SAMSUNG_DEV_PWM
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help
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Use the High Resolution timer support
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config S5P_PM
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bool
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help
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Common code for power management support on S5P and newer SoCs
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Note: Do not select this for S5P6440 and S5P6450.
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comment "System MMU"
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config S5P_SYSTEM_MMU
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bool "S5P SYSTEM MMU"
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depends on ARCH_EXYNOS4
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help
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Say Y here if you want to enable System MMU
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config S5P_SLEEP
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bool
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help
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Internal config node to apply common S5P sleep management code.
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Can be selected by S5P and newer SoCs with similar sleep procedure.
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config S5P_DEV_FIMC0
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bool
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help
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Compile in platform device definitions for FIMC controller 0
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config S5P_DEV_FIMC1
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bool
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help
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Compile in platform device definitions for FIMC controller 1
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config S5P_DEV_FIMC2
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bool
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help
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Compile in platform device definitions for FIMC controller 2
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config S5P_DEV_FIMC3
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bool
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help
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Compile in platform device definitions for FIMC controller 3
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config S5P_DEV_FIMD0
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bool
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help
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Compile in platform device definitions for FIMD controller 0
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config S5P_DEV_I2C_HDMIPHY
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bool
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help
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Compile in platform device definitions for I2C HDMIPHY controller
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config S5P_DEV_MFC
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bool
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help
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Compile in platform device definitions for MFC
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config S5P_DEV_ONENAND
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bool
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help
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Compile in platform device definition for OneNAND controller
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config S5P_DEV_CSIS0
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bool
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help
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Compile in platform device definitions for MIPI-CSIS channel 0
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config S5P_DEV_CSIS1
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bool
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help
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Compile in platform device definitions for MIPI-CSIS channel 1
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config S5P_DEV_TV
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bool
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help
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Compile in platform device definition for TV interface
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config S5P_DEV_USB_EHCI
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bool
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help
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Compile in platform device definition for USB EHCI
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config S5P_SETUP_MIPIPHY
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bool
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help
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Compile in common setup code for MIPI-CSIS and MIPI-DSIM devices
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