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b721243a67
Patch from Lennert Buytenhek Remove the ixdp2x01 cs89x0 hack from ixp2000's io implementation. Since the cs89x0 driver has been made properly aware of the odd way the cs89x0 is hooked up on the ixdp2x01, we don't need this hack anymore. Signed-off-by: Lennert Buytenhek <buytenh@wantstofly.org> Signed-off-by: Deepak Saxena <dsaxena@plexity.net> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
135 lines
3.5 KiB
C
135 lines
3.5 KiB
C
/*
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* linux/include/asm-arm/arch-ixp2000/io.h
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*
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* Original Author: Naeem M Afzal <naeem.m.afzal@intel.com>
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* Maintainer: Deepak Saxena <dsaxena@plexity.net>
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*
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* Copyright (C) 2002 Intel Corp.
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* Copyrgiht (C) 2003-2004 MontaVista Software, Inc.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#ifndef __ASM_ARM_ARCH_IO_H
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#define __ASM_ARM_ARCH_IO_H
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#include <asm/hardware.h>
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#define IO_SPACE_LIMIT 0xffffffff
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#define __mem_pci(a) (a)
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/*
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* The A? revisions of the IXP2000s assert byte lanes for PCI I/O
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* transactions the other way round (MEM transactions don't have this
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* issue), so if we want to support those models, we need to override
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* the standard I/O functions.
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*
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* B0 and later have a bit that can be set to 1 to get the proper
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* behavior for I/O transactions, which then allows us to use the
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* standard I/O functions. This is what we do if the user does not
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* explicitly ask for support for pre-B0.
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*/
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#ifdef CONFIG_IXP2000_SUPPORT_BROKEN_PCI_IO
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#define ___io(p) ((void __iomem *)((p)+IXP2000_PCI_IO_VIRT_BASE))
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#define alignb(addr) (void __iomem *)((unsigned long)(addr) ^ 3)
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#define alignw(addr) (void __iomem *)((unsigned long)(addr) ^ 2)
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#define outb(v,p) __raw_writeb((v),alignb(___io(p)))
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#define outw(v,p) __raw_writew((v),alignw(___io(p)))
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#define outl(v,p) __raw_writel((v),___io(p))
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#define inb(p) ({ unsigned int __v = __raw_readb(alignb(___io(p))); __v; })
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#define inw(p) \
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({ unsigned int __v = (__raw_readw(alignw(___io(p)))); __v; })
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#define inl(p) \
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({ unsigned int __v = (__raw_readl(___io(p))); __v; })
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#define outsb(p,d,l) __raw_writesb(alignb(___io(p)),d,l)
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#define outsw(p,d,l) __raw_writesw(alignw(___io(p)),d,l)
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#define outsl(p,d,l) __raw_writesl(___io(p),d,l)
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#define insb(p,d,l) __raw_readsb(alignb(___io(p)),d,l)
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#define insw(p,d,l) __raw_readsw(alignw(___io(p)),d,l)
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#define insl(p,d,l) __raw_readsl(___io(p),d,l)
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#define __is_io_address(p) ((((unsigned long)(p)) & ~(IXP2000_PCI_IO_SIZE - 1)) == IXP2000_PCI_IO_VIRT_BASE)
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#define ioread8(p) \
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({ \
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unsigned int __v; \
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\
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if (__is_io_address(p)) { \
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__v = __raw_readb(alignb(p)); \
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} else { \
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__v = __raw_readb(p); \
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} \
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\
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__v; \
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}) \
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#define ioread16(p) \
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({ \
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unsigned int __v; \
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\
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if (__is_io_address(p)) { \
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__v = __raw_readw(alignw(p)); \
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} else { \
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__v = le16_to_cpu(__raw_readw(p)); \
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} \
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\
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__v; \
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})
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#define ioread32(p) \
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({ \
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unsigned int __v; \
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\
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if (__is_io_address(p)) { \
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__v = __raw_readl(p); \
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} else { \
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__v = le32_to_cpu(__raw_readl(p)); \
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} \
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\
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__v; \
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})
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#define iowrite8(v,p) \
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({ \
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if (__is_io_address(p)) { \
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__raw_writeb((v), alignb(p)); \
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} else { \
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__raw_writeb((v), p); \
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} \
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})
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#define iowrite16(v,p) \
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({ \
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if (__is_io_address(p)) { \
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__raw_writew((v), alignw(p)); \
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} else { \
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__raw_writew(cpu_to_le16(v), p); \
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} \
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})
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#define iowrite32(v,p) \
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({ \
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if (__is_io_address(p)) { \
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__raw_writel((v), p); \
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} else { \
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__raw_writel(cpu_to_le32(v), p); \
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} \
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})
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#define ioport_map(port, nr) ___io(port)
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#define ioport_unmap(addr)
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#else
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#define __io(p) ((void __iomem *)((p)+IXP2000_PCI_IO_VIRT_BASE))
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#endif
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#endif
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