mirror of
https://github.com/edk2-porting/linux-next.git
synced 2024-12-25 21:54:06 +08:00
1da177e4c3
Initial git repository build. I'm not bothering with the full history, even though we have it. We can create a separate "historical" git archive of that later if we want to, and in the meantime it's about 3.2GB when imported into git - space that would just make the early git days unnecessarily complicated, when we don't have a lot of good infrastructure for it. Let it rip!
79 lines
2.5 KiB
C
79 lines
2.5 KiB
C
/*
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* AUTCPU12 specific defines
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*
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* (c) 2001 Thomas Gleixner, autronix automation <gleixner@autronix.de>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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*/
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#ifndef __ASM_ARCH_AUTCPU12_H
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#define __ASM_ARCH_AUTCPU12_H
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/*
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* The CS8900A ethernet chip has its I/O registers wired to chip select 2
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* (nCS2). This is the mapping for it.
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*/
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#define AUTCPU12_PHYS_CS8900A CS2_PHYS_BASE /* physical */
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#define AUTCPU12_VIRT_CS8900A (0xfe000000) /* virtual */
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/*
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* The flash bank is wired to chip select 0
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*/
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#define AUTCPU12_PHYS_FLASH CS0_PHYS_BASE /* physical */
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/* offset for device specific information structure */
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#define AUTCPU12_LCDINFO_OFFS (0x00010000)
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/*
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* Videomemory is the internal SRAM (CS 6)
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*/
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#define AUTCPU12_PHYS_VIDEO CS6_PHYS_BASE
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#define AUTCPU12_VIRT_VIDEO (0xfd000000)
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/*
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* All special IO's are tied to CS1
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*/
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#define AUTCPU12_PHYS_CHAR_LCD CS1_PHYS_BASE +0x00000000 /* physical */
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#define AUTCPU12_PHYS_NVRAM CS1_PHYS_BASE +0x02000000 /* physical */
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#define AUTCPU12_PHYS_CSAUX1 CS1_PHYS_BASE +0x04000000 /* physical */
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#define AUTCPU12_PHYS_SMC CS1_PHYS_BASE +0x06000000 /* physical */
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#define AUTCPU12_PHYS_CAN CS1_PHYS_BASE +0x08000000 /* physical */
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#define AUTCPU12_PHYS_TOUCH CS1_PHYS_BASE +0x0A000000 /* physical */
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#define AUTCPU12_PHYS_IO CS1_PHYS_BASE +0x0C000000 /* physical */
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#define AUTCPU12_PHYS_LPT CS1_PHYS_BASE +0x0E000000 /* physical */
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/*
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* defines for smartmedia card access
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*/
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#define AUTCPU12_SMC_RDY (1<<2)
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#define AUTCPU12_SMC_ALE (1<<3)
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#define AUTCPU12_SMC_CLE (1<<4)
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#define AUTCPU12_SMC_PORT_OFFSET PBDR
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#define AUTCPU12_SMC_SELECT_OFFSET 0x10
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/*
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* defines for lcd contrast
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*/
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#define AUTCPU12_DPOT_PORT_OFFSET PEDR
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#define AUTCPU12_DPOT_CS (1<<0)
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#define AUTCPU12_DPOT_CLK (1<<1)
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#define AUTCPU12_DPOT_UD (1<<2)
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#endif
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