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197858b685
stm32mp1 RCC IP 1 has a reset SET register and a reset CLEAR register. Writing '0' on reset SET register has no effect Writing '1' on reset SET register activates the reset of the corresponding peripheral Writing '0' on reset CLEAR register has no effect Writing '1' on reset CLEAR register releases the reset of the corresponding peripheral See Documentation/devicetree/bindings/clock/st,stm32mp1-rcc.txt Signed-off-by: Gabriel Fernandez <gabriel.fernandez@st.com> Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
116 lines
2.8 KiB
C
116 lines
2.8 KiB
C
// SPDX-License-Identifier: GPL-2.0
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/*
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* Copyright (C) STMicroelectronics 2018 - All Rights Reserved
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* Author: Gabriel Fernandez <gabriel.fernandez@st.com> for STMicroelectronics.
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*/
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#include <linux/device.h>
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#include <linux/err.h>
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#include <linux/io.h>
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#include <linux/of.h>
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#include <linux/platform_device.h>
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#include <linux/reset-controller.h>
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#define CLR_OFFSET 0x4
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struct stm32_reset_data {
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struct reset_controller_dev rcdev;
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void __iomem *membase;
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};
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static inline struct stm32_reset_data *
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to_stm32_reset_data(struct reset_controller_dev *rcdev)
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{
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return container_of(rcdev, struct stm32_reset_data, rcdev);
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}
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static int stm32_reset_update(struct reset_controller_dev *rcdev,
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unsigned long id, bool assert)
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{
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struct stm32_reset_data *data = to_stm32_reset_data(rcdev);
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int reg_width = sizeof(u32);
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int bank = id / (reg_width * BITS_PER_BYTE);
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int offset = id % (reg_width * BITS_PER_BYTE);
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void __iomem *addr;
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addr = data->membase + (bank * reg_width);
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if (!assert)
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addr += CLR_OFFSET;
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writel(BIT(offset), addr);
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return 0;
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}
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static int stm32_reset_assert(struct reset_controller_dev *rcdev,
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unsigned long id)
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{
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return stm32_reset_update(rcdev, id, true);
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}
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static int stm32_reset_deassert(struct reset_controller_dev *rcdev,
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unsigned long id)
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{
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return stm32_reset_update(rcdev, id, false);
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}
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static int stm32_reset_status(struct reset_controller_dev *rcdev,
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unsigned long id)
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{
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struct stm32_reset_data *data = to_stm32_reset_data(rcdev);
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int reg_width = sizeof(u32);
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int bank = id / (reg_width * BITS_PER_BYTE);
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int offset = id % (reg_width * BITS_PER_BYTE);
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u32 reg;
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reg = readl(data->membase + (bank * reg_width));
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return !!(reg & BIT(offset));
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}
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static const struct reset_control_ops stm32_reset_ops = {
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.assert = stm32_reset_assert,
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.deassert = stm32_reset_deassert,
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.status = stm32_reset_status,
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};
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static const struct of_device_id stm32_reset_dt_ids[] = {
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{ .compatible = "st,stm32mp1-rcc"},
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{ /* sentinel */ },
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};
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static int stm32_reset_probe(struct platform_device *pdev)
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{
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struct device *dev = &pdev->dev;
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struct stm32_reset_data *data;
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void __iomem *membase;
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struct resource *res;
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data = devm_kzalloc(dev, sizeof(*data), GFP_KERNEL);
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if (!data)
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return -ENOMEM;
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res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
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membase = devm_ioremap_resource(dev, res);
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if (IS_ERR(membase))
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return PTR_ERR(membase);
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data->membase = membase;
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data->rcdev.owner = THIS_MODULE;
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data->rcdev.nr_resets = resource_size(res) * BITS_PER_BYTE;
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data->rcdev.ops = &stm32_reset_ops;
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data->rcdev.of_node = dev->of_node;
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return devm_reset_controller_register(dev, &data->rcdev);
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}
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static struct platform_driver stm32_reset_driver = {
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.probe = stm32_reset_probe,
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.driver = {
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.name = "stm32mp1-reset",
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.of_match_table = stm32_reset_dt_ids,
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},
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};
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builtin_platform_driver(stm32_reset_driver);
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