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92618ff8b0
OMAP2xxx devices have two on-chip APLLs. These APLLs can automatically enter idle when not in use. Connect the APLL autoidle code to the clock code, so that the clock framework can handle this process. As part of this patch, remove the code in mach-omap2/pm24xx.c that previously handled APLL autoidle control. Signed-off-by: Paul Walmsley <paul@pwsan.com> Cc: Kevin Hilman <khilman@ti.com> Tested-by: Rajendra Nayak <rnayak@ti.com> Reviewed-by: Kevin Hilman <khilman@ti.com>
147 lines
3.2 KiB
C
147 lines
3.2 KiB
C
/*
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* OMAP2xxx APLL clock control functions
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*
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* Copyright (C) 2005-2008 Texas Instruments, Inc.
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* Copyright (C) 2004-2010 Nokia Corporation
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*
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* Contacts:
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* Richard Woodruff <r-woodruff2@ti.com>
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* Paul Walmsley
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*
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* Based on earlier work by Tuukka Tikkanen, Tony Lindgren,
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* Gordon McNutt and RidgeRun, Inc.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#undef DEBUG
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#include <linux/kernel.h>
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#include <linux/clk.h>
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#include <linux/io.h>
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#include <plat/clock.h>
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#include <plat/prcm.h>
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#include "clock.h"
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#include "clock2xxx.h"
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#include "cm2xxx_3xxx.h"
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#include "cm-regbits-24xx.h"
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/* CM_CLKEN_PLL.EN_{54,96}M_PLL options (24XX) */
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#define EN_APLL_STOPPED 0
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#define EN_APLL_LOCKED 3
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/* CM_CLKSEL1_PLL.APLLS_CLKIN options (24XX) */
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#define APLLS_CLKIN_19_2MHZ 0
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#define APLLS_CLKIN_13MHZ 2
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#define APLLS_CLKIN_12MHZ 3
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void __iomem *cm_idlest_pll;
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/* Private functions */
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/* Enable an APLL if off */
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static int omap2_clk_apll_enable(struct clk *clk, u32 status_mask)
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{
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u32 cval, apll_mask;
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apll_mask = EN_APLL_LOCKED << clk->enable_bit;
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cval = omap2_cm_read_mod_reg(PLL_MOD, CM_CLKEN);
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if ((cval & apll_mask) == apll_mask)
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return 0; /* apll already enabled */
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cval &= ~apll_mask;
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cval |= apll_mask;
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omap2_cm_write_mod_reg(cval, PLL_MOD, CM_CLKEN);
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omap2_cm_wait_idlest(cm_idlest_pll, status_mask,
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OMAP24XX_CM_IDLEST_VAL, clk->name);
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/*
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* REVISIT: Should we return an error code if omap2_wait_clock_ready()
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* fails?
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*/
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return 0;
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}
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static int omap2_clk_apll96_enable(struct clk *clk)
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{
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return omap2_clk_apll_enable(clk, OMAP24XX_ST_96M_APLL_MASK);
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}
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static int omap2_clk_apll54_enable(struct clk *clk)
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{
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return omap2_clk_apll_enable(clk, OMAP24XX_ST_54M_APLL_MASK);
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}
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static void _apll96_allow_idle(struct clk *clk)
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{
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omap2xxx_cm_set_apll96_auto_low_power_stop();
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}
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static void _apll96_deny_idle(struct clk *clk)
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{
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omap2xxx_cm_set_apll96_disable_autoidle();
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}
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static void _apll54_allow_idle(struct clk *clk)
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{
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omap2xxx_cm_set_apll54_auto_low_power_stop();
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}
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static void _apll54_deny_idle(struct clk *clk)
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{
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omap2xxx_cm_set_apll54_disable_autoidle();
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}
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/* Stop APLL */
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static void omap2_clk_apll_disable(struct clk *clk)
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{
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u32 cval;
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cval = omap2_cm_read_mod_reg(PLL_MOD, CM_CLKEN);
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cval &= ~(EN_APLL_LOCKED << clk->enable_bit);
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omap2_cm_write_mod_reg(cval, PLL_MOD, CM_CLKEN);
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}
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/* Public data */
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const struct clkops clkops_apll96 = {
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.enable = omap2_clk_apll96_enable,
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.disable = omap2_clk_apll_disable,
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.allow_idle = _apll96_allow_idle,
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.deny_idle = _apll96_deny_idle,
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};
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const struct clkops clkops_apll54 = {
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.enable = omap2_clk_apll54_enable,
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.disable = omap2_clk_apll_disable,
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.allow_idle = _apll54_allow_idle,
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.deny_idle = _apll54_deny_idle,
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};
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/* Public functions */
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u32 omap2xxx_get_apll_clkin(void)
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{
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u32 aplls, srate = 0;
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aplls = omap2_cm_read_mod_reg(PLL_MOD, CM_CLKSEL1);
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aplls &= OMAP24XX_APLLS_CLKIN_MASK;
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aplls >>= OMAP24XX_APLLS_CLKIN_SHIFT;
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if (aplls == APLLS_CLKIN_19_2MHZ)
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srate = 19200000;
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else if (aplls == APLLS_CLKIN_13MHZ)
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srate = 13000000;
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else if (aplls == APLLS_CLKIN_12MHZ)
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srate = 12000000;
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return srate;
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}
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