mirror of
https://github.com/edk2-porting/linux-next.git
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ce0eff0d9b
We want to use DW AXI DMAC on HSDK board in our automated verification to test cache & dma kernel code changes. This is perfect candidate as we don't depend on any external peripherals like MMC card / USB storage / etc. To increase test coverage we want to test both options: * DW AXI DMAC is connected through IOC port & dma direct ops used * DW AXI DMAC is connected to DDR port & dma noncoherent ops used Introduce 'arc_hsdk_axi_dmac_coherent' global variable which can be modified by debugger (same way as we patch 'ioc_enable') to switch between these options without recompiling the kernel. Depend on this value we tweak memory bridge configuration and "dma-coherent" DTS property of DW AXI DMAC. Signed-off-by: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com> Acked-by: Alexey Brodkin <abrodkin@synopsys.com> Signed-off-by: Vineet Gupta <vgupta@synopsys.com>
344 lines
11 KiB
C
344 lines
11 KiB
C
// SPDX-License-Identifier: GPL-2.0-only
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/*
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* ARC HSDK Platform support code
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*
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* Copyright (C) 2017 Synopsys, Inc. (www.synopsys.com)
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*/
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#include <linux/init.h>
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#include <linux/of_fdt.h>
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#include <linux/libfdt.h>
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#include <linux/smp.h>
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#include <asm/arcregs.h>
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#include <asm/io.h>
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#include <asm/mach_desc.h>
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int arc_hsdk_axi_dmac_coherent __section(.data) = 0;
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#define ARC_CCM_UNUSED_ADDR 0x60000000
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static void __init hsdk_init_per_cpu(unsigned int cpu)
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{
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/*
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* By default ICCM is mapped to 0x7z while this area is used for
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* kernel virtual mappings, so move it to currently unused area.
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*/
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if (cpuinfo_arc700[cpu].iccm.sz)
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write_aux_reg(ARC_REG_AUX_ICCM, ARC_CCM_UNUSED_ADDR);
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/*
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* By default DCCM is mapped to 0x8z while this area is used by kernel,
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* so move it to currently unused area.
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*/
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if (cpuinfo_arc700[cpu].dccm.sz)
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write_aux_reg(ARC_REG_AUX_DCCM, ARC_CCM_UNUSED_ADDR);
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}
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#define ARC_PERIPHERAL_BASE 0xf0000000
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#define CREG_BASE (ARC_PERIPHERAL_BASE + 0x1000)
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#define SDIO_BASE (ARC_PERIPHERAL_BASE + 0xA000)
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#define SDIO_UHS_REG_EXT (SDIO_BASE + 0x108)
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#define SDIO_UHS_REG_EXT_DIV_2 (2 << 30)
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#define HSDK_GPIO_INTC (ARC_PERIPHERAL_BASE + 0x3000)
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static void __init hsdk_enable_gpio_intc_wire(void)
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{
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/*
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* Peripherals on CPU Card are wired to cpu intc via intermediate
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* DW APB GPIO blocks (mainly for debouncing)
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*
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* ---------------------
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* | snps,archs-intc |
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* ---------------------
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* |
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* ----------------------
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* | snps,archs-idu-intc |
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* ----------------------
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* | | | | |
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* | [eth] [USB] [... other peripherals]
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* |
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* -------------------
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* | snps,dw-apb-intc |
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* -------------------
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* | | | |
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* [Bt] [HAPS] [... other peripherals]
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*
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* Current implementation of "irq-dw-apb-ictl" driver doesn't work well
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* with stacked INTCs. In particular problem happens if its master INTC
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* not yet instantiated. See discussion here -
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* https://lkml.org/lkml/2015/3/4/755
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*
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* So setup the first gpio block as a passive pass thru and hide it from
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* DT hardware topology - connect intc directly to cpu intc
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* The GPIO "wire" needs to be init nevertheless (here)
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*
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* One side adv is that peripheral interrupt handling avoids one nested
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* intc ISR hop
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*
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* According to HSDK User's Manual [1], "Table 2 Interrupt Mapping"
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* we have the following GPIO input lines used as sources of interrupt:
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* - GPIO[0] - Bluetooth interrupt of RS9113 module
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* - GPIO[2] - HAPS interrupt (on HapsTrak 3 connector)
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* - GPIO[3] - Audio codec (MAX9880A) interrupt
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* - GPIO[8-23] - Available on Arduino and PMOD_x headers
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* For now there's no use of Arduino and PMOD_x headers in Linux
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* use-case so we only enable lines 0, 2 and 3.
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*
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* [1] https://github.com/foss-for-synopsys-dwc-arc-processors/ARC-Development-Systems-Forum/wiki/docs/ARC_HSDK_User_Guide.pdf
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*/
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#define GPIO_INTEN (HSDK_GPIO_INTC + 0x30)
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#define GPIO_INTMASK (HSDK_GPIO_INTC + 0x34)
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#define GPIO_INTTYPE_LEVEL (HSDK_GPIO_INTC + 0x38)
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#define GPIO_INT_POLARITY (HSDK_GPIO_INTC + 0x3c)
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#define GPIO_INT_CONNECTED_MASK 0x0d
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iowrite32(0xffffffff, (void __iomem *) GPIO_INTMASK);
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iowrite32(~GPIO_INT_CONNECTED_MASK, (void __iomem *) GPIO_INTMASK);
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iowrite32(0x00000000, (void __iomem *) GPIO_INTTYPE_LEVEL);
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iowrite32(0xffffffff, (void __iomem *) GPIO_INT_POLARITY);
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iowrite32(GPIO_INT_CONNECTED_MASK, (void __iomem *) GPIO_INTEN);
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}
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static int __init hsdk_tweak_node_coherency(const char *path, bool coherent)
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{
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void *fdt = initial_boot_params;
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const void *prop;
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int node, ret;
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bool dt_coh_set;
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node = fdt_path_offset(fdt, path);
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if (node < 0)
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goto tweak_fail;
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prop = fdt_getprop(fdt, node, "dma-coherent", &ret);
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if (!prop && ret != -FDT_ERR_NOTFOUND)
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goto tweak_fail;
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dt_coh_set = ret != -FDT_ERR_NOTFOUND;
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ret = 0;
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/* need to remove "dma-coherent" property */
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if (dt_coh_set && !coherent)
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ret = fdt_delprop(fdt, node, "dma-coherent");
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/* need to set "dma-coherent" property */
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if (!dt_coh_set && coherent)
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ret = fdt_setprop(fdt, node, "dma-coherent", NULL, 0);
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if (ret < 0)
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goto tweak_fail;
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return 0;
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tweak_fail:
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pr_err("failed to tweak %s to %scoherent\n", path, coherent ? "" : "non");
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return -EFAULT;
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}
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enum hsdk_axi_masters {
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M_HS_CORE = 0,
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M_HS_RTT,
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M_AXI_TUN,
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M_HDMI_VIDEO,
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M_HDMI_AUDIO,
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M_USB_HOST,
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M_ETHERNET,
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M_SDIO,
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M_GPU,
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M_DMAC_0,
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M_DMAC_1,
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M_DVFS
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};
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#define UPDATE_VAL 1
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/*
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* This is modified configuration of AXI bridge. Default settings
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* are specified in "Table 111 CREG Address Decoder register reset values".
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*
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* AXI_M_m_SLV{0|1} - Slave Select register for master 'm'.
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* Possible slaves are:
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* - 0 => no slave selected
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* - 1 => DDR controller port #1
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* - 2 => SRAM controller
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* - 3 => AXI tunnel
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* - 4 => EBI controller
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* - 5 => ROM controller
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* - 6 => AXI2APB bridge
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* - 7 => DDR controller port #2
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* - 8 => DDR controller port #3
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* - 9 => HS38x4 IOC
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* - 10 => HS38x4 DMI
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* AXI_M_m_OFFSET{0|1} - Addr Offset register for master 'm'
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*
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* Please read ARC HS Development IC Specification, section 17.2 for more
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* information about apertures configuration.
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*
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* m master AXI_M_m_SLV0 AXI_M_m_SLV1 AXI_M_m_OFFSET0 AXI_M_m_OFFSET1
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* 0 HS (CBU) 0x11111111 0x63111111 0xFEDCBA98 0x0E543210
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* 1 HS (RTT) 0x77777777 0x77777777 0xFEDCBA98 0x76543210
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* 2 AXI Tunnel 0x88888888 0x88888888 0xFEDCBA98 0x76543210
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* 3 HDMI-VIDEO 0x77777777 0x77777777 0xFEDCBA98 0x76543210
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* 4 HDMI-ADUIO 0x77777777 0x77777777 0xFEDCBA98 0x76543210
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* 5 USB-HOST 0x77777777 0x77999999 0xFEDCBA98 0x76DCBA98
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* 6 ETHERNET 0x77777777 0x77999999 0xFEDCBA98 0x76DCBA98
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* 7 SDIO 0x77777777 0x77999999 0xFEDCBA98 0x76DCBA98
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* 8 GPU 0x77777777 0x77777777 0xFEDCBA98 0x76543210
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* 9 DMAC (port #1) 0x77777777 0x77777777 0xFEDCBA98 0x76543210
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* 10 DMAC (port #2) 0x77777777 0x77777777 0xFEDCBA98 0x76543210
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* 11 DVFS 0x00000000 0x60000000 0x00000000 0x00000000
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*/
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#define CREG_AXI_M_SLV0(m) ((void __iomem *)(CREG_BASE + 0x20 * (m)))
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#define CREG_AXI_M_SLV1(m) ((void __iomem *)(CREG_BASE + 0x20 * (m) + 0x04))
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#define CREG_AXI_M_OFT0(m) ((void __iomem *)(CREG_BASE + 0x20 * (m) + 0x08))
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#define CREG_AXI_M_OFT1(m) ((void __iomem *)(CREG_BASE + 0x20 * (m) + 0x0C))
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#define CREG_AXI_M_UPDT(m) ((void __iomem *)(CREG_BASE + 0x20 * (m) + 0x14))
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#define CREG_AXI_M_HS_CORE_BOOT ((void __iomem *)(CREG_BASE + 0x010))
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#define CREG_PAE ((void __iomem *)(CREG_BASE + 0x180))
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#define CREG_PAE_UPDT ((void __iomem *)(CREG_BASE + 0x194))
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static void __init hsdk_init_memory_bridge_axi_dmac(void)
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{
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bool coherent = !!arc_hsdk_axi_dmac_coherent;
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u32 axi_m_slv1, axi_m_oft1;
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/*
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* Don't tweak memory bridge configuration if we failed to tweak DTB
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* as we will end up in a inconsistent state.
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*/
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if (hsdk_tweak_node_coherency("/soc/dmac@80000", coherent))
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return;
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if (coherent) {
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axi_m_slv1 = 0x77999999;
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axi_m_oft1 = 0x76DCBA98;
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} else {
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axi_m_slv1 = 0x77777777;
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axi_m_oft1 = 0x76543210;
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}
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writel(0x77777777, CREG_AXI_M_SLV0(M_DMAC_0));
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writel(0xFEDCBA98, CREG_AXI_M_OFT0(M_DMAC_0));
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writel(axi_m_slv1, CREG_AXI_M_SLV1(M_DMAC_0));
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writel(axi_m_oft1, CREG_AXI_M_OFT1(M_DMAC_0));
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writel(UPDATE_VAL, CREG_AXI_M_UPDT(M_DMAC_0));
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writel(0x77777777, CREG_AXI_M_SLV0(M_DMAC_1));
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writel(0xFEDCBA98, CREG_AXI_M_OFT0(M_DMAC_1));
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writel(axi_m_slv1, CREG_AXI_M_SLV1(M_DMAC_1));
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writel(axi_m_oft1, CREG_AXI_M_OFT1(M_DMAC_1));
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writel(UPDATE_VAL, CREG_AXI_M_UPDT(M_DMAC_1));
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}
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static void __init hsdk_init_memory_bridge(void)
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{
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u32 reg;
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/*
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* M_HS_CORE has one unique register - BOOT.
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* We need to clean boot mirror (BOOT[1:0]) bits in them to avoid first
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* aperture to be masked by 'boot mirror'.
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*/
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reg = readl(CREG_AXI_M_HS_CORE_BOOT) & (~0x3);
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writel(reg, CREG_AXI_M_HS_CORE_BOOT);
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writel(0x11111111, CREG_AXI_M_SLV0(M_HS_CORE));
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writel(0x63111111, CREG_AXI_M_SLV1(M_HS_CORE));
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writel(0xFEDCBA98, CREG_AXI_M_OFT0(M_HS_CORE));
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writel(0x0E543210, CREG_AXI_M_OFT1(M_HS_CORE));
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writel(UPDATE_VAL, CREG_AXI_M_UPDT(M_HS_CORE));
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writel(0x77777777, CREG_AXI_M_SLV0(M_HS_RTT));
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writel(0x77777777, CREG_AXI_M_SLV1(M_HS_RTT));
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writel(0xFEDCBA98, CREG_AXI_M_OFT0(M_HS_RTT));
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writel(0x76543210, CREG_AXI_M_OFT1(M_HS_RTT));
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writel(UPDATE_VAL, CREG_AXI_M_UPDT(M_HS_RTT));
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writel(0x88888888, CREG_AXI_M_SLV0(M_AXI_TUN));
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writel(0x88888888, CREG_AXI_M_SLV1(M_AXI_TUN));
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writel(0xFEDCBA98, CREG_AXI_M_OFT0(M_AXI_TUN));
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writel(0x76543210, CREG_AXI_M_OFT1(M_AXI_TUN));
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writel(UPDATE_VAL, CREG_AXI_M_UPDT(M_AXI_TUN));
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writel(0x77777777, CREG_AXI_M_SLV0(M_HDMI_VIDEO));
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writel(0x77777777, CREG_AXI_M_SLV1(M_HDMI_VIDEO));
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writel(0xFEDCBA98, CREG_AXI_M_OFT0(M_HDMI_VIDEO));
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writel(0x76543210, CREG_AXI_M_OFT1(M_HDMI_VIDEO));
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writel(UPDATE_VAL, CREG_AXI_M_UPDT(M_HDMI_VIDEO));
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writel(0x77777777, CREG_AXI_M_SLV0(M_HDMI_AUDIO));
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writel(0x77777777, CREG_AXI_M_SLV1(M_HDMI_AUDIO));
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writel(0xFEDCBA98, CREG_AXI_M_OFT0(M_HDMI_AUDIO));
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writel(0x76543210, CREG_AXI_M_OFT1(M_HDMI_AUDIO));
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writel(UPDATE_VAL, CREG_AXI_M_UPDT(M_HDMI_AUDIO));
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writel(0x77777777, CREG_AXI_M_SLV0(M_USB_HOST));
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writel(0x77999999, CREG_AXI_M_SLV1(M_USB_HOST));
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writel(0xFEDCBA98, CREG_AXI_M_OFT0(M_USB_HOST));
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writel(0x76DCBA98, CREG_AXI_M_OFT1(M_USB_HOST));
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writel(UPDATE_VAL, CREG_AXI_M_UPDT(M_USB_HOST));
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writel(0x77777777, CREG_AXI_M_SLV0(M_ETHERNET));
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writel(0x77999999, CREG_AXI_M_SLV1(M_ETHERNET));
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writel(0xFEDCBA98, CREG_AXI_M_OFT0(M_ETHERNET));
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writel(0x76DCBA98, CREG_AXI_M_OFT1(M_ETHERNET));
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writel(UPDATE_VAL, CREG_AXI_M_UPDT(M_ETHERNET));
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writel(0x77777777, CREG_AXI_M_SLV0(M_SDIO));
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writel(0x77999999, CREG_AXI_M_SLV1(M_SDIO));
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writel(0xFEDCBA98, CREG_AXI_M_OFT0(M_SDIO));
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writel(0x76DCBA98, CREG_AXI_M_OFT1(M_SDIO));
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writel(UPDATE_VAL, CREG_AXI_M_UPDT(M_SDIO));
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writel(0x77777777, CREG_AXI_M_SLV0(M_GPU));
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writel(0x77777777, CREG_AXI_M_SLV1(M_GPU));
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writel(0xFEDCBA98, CREG_AXI_M_OFT0(M_GPU));
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writel(0x76543210, CREG_AXI_M_OFT1(M_GPU));
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writel(UPDATE_VAL, CREG_AXI_M_UPDT(M_GPU));
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writel(0x00000000, CREG_AXI_M_SLV0(M_DVFS));
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writel(0x60000000, CREG_AXI_M_SLV1(M_DVFS));
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writel(0x00000000, CREG_AXI_M_OFT0(M_DVFS));
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writel(0x00000000, CREG_AXI_M_OFT1(M_DVFS));
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writel(UPDATE_VAL, CREG_AXI_M_UPDT(M_DVFS));
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hsdk_init_memory_bridge_axi_dmac();
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/*
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* PAE remapping for DMA clients does not work due to an RTL bug, so
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* CREG_PAE register must be programmed to all zeroes, otherwise it
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* will cause problems with DMA to/from peripherals even if PAE40 is
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* not used.
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*/
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writel(0x00000000, CREG_PAE);
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writel(UPDATE_VAL, CREG_PAE_UPDT);
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}
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static void __init hsdk_init_early(void)
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{
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hsdk_init_memory_bridge();
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/*
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* Switch SDIO external ciu clock divider from default div-by-8 to
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* minimum possible div-by-2.
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*/
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iowrite32(SDIO_UHS_REG_EXT_DIV_2, (void __iomem *) SDIO_UHS_REG_EXT);
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hsdk_enable_gpio_intc_wire();
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}
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static const char *hsdk_compat[] __initconst = {
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"snps,hsdk",
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NULL,
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};
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MACHINE_START(SIMULATION, "hsdk")
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.dt_compat = hsdk_compat,
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.init_early = hsdk_init_early,
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.init_per_cpu = hsdk_init_per_cpu,
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MACHINE_END
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