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5aaf254409
MVFR0 and MVFR1 are only available starting with ARM1136 r1p0 release according to "B.5 VFP changes" in DDI0211F_arm1136_r1p0_trm.pdf. This is also when TLS register got added, so we can use HAS_TLS also to test for MVFR0 and MVFR1. Otherwise VFPFMRX and VFPFMXR access fails and we get: Internal error: Oops - undefined instruction: 0 [#1] PC is at no_old_VFP_process+0x8/0x3c LR is at __und_svc+0x48/0x80 ... Signed-off-by: Tony Lindgren <tony@atomide.com> Acked-by: Catalin Marinas <catalin.marinas@arm.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
66 lines
2.1 KiB
C
66 lines
2.1 KiB
C
/*
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* arch/arm/include/asm/vfpmacros.h
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*
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* Assembler-only file containing VFP macros and register definitions.
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*/
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#include <asm/hwcap.h>
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#include "vfp.h"
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@ Macros to allow building with old toolkits (with no VFP support)
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.macro VFPFMRX, rd, sysreg, cond
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MRC\cond p10, 7, \rd, \sysreg, cr0, 0 @ FMRX \rd, \sysreg
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.endm
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.macro VFPFMXR, sysreg, rd, cond
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MCR\cond p10, 7, \rd, \sysreg, cr0, 0 @ FMXR \sysreg, \rd
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.endm
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@ read all the working registers back into the VFP
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.macro VFPFLDMIA, base, tmp
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#if __LINUX_ARM_ARCH__ < 6
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LDC p11, cr0, [\base],#33*4 @ FLDMIAX \base!, {d0-d15}
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#else
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LDC p11, cr0, [\base],#32*4 @ FLDMIAD \base!, {d0-d15}
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#endif
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#ifdef CONFIG_VFPv3
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#if __LINUX_ARM_ARCH__ <= 6
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ldr \tmp, =elf_hwcap @ may not have MVFR regs
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ldr \tmp, [\tmp, #0]
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tst \tmp, #HWCAP_VFPv3D16
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ldceq p11, cr0, [\base],#32*4 @ FLDMIAD \base!, {d16-d31}
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addne \base, \base, #32*4 @ step over unused register space
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#else
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VFPFMRX \tmp, MVFR0 @ Media and VFP Feature Register 0
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and \tmp, \tmp, #MVFR0_A_SIMD_MASK @ A_SIMD field
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cmp \tmp, #2 @ 32 x 64bit registers?
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ldceql p11, cr0, [\base],#32*4 @ FLDMIAD \base!, {d16-d31}
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addne \base, \base, #32*4 @ step over unused register space
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#endif
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#endif
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.endm
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@ write all the working registers out of the VFP
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.macro VFPFSTMIA, base, tmp
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#if __LINUX_ARM_ARCH__ < 6
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STC p11, cr0, [\base],#33*4 @ FSTMIAX \base!, {d0-d15}
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#else
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STC p11, cr0, [\base],#32*4 @ FSTMIAD \base!, {d0-d15}
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#endif
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#ifdef CONFIG_VFPv3
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#if __LINUX_ARM_ARCH__ <= 6
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ldr \tmp, =elf_hwcap @ may not have MVFR regs
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ldr \tmp, [\tmp, #0]
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tst \tmp, #HWCAP_VFPv3D16
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stceq p11, cr0, [\base],#32*4 @ FSTMIAD \base!, {d16-d31}
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addne \base, \base, #32*4 @ step over unused register space
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#else
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VFPFMRX \tmp, MVFR0 @ Media and VFP Feature Register 0
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and \tmp, \tmp, #MVFR0_A_SIMD_MASK @ A_SIMD field
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cmp \tmp, #2 @ 32 x 64bit registers?
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stceql p11, cr0, [\base],#32*4 @ FSTMIAD \base!, {d16-d31}
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addne \base, \base, #32*4 @ step over unused register space
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#endif
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#endif
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.endm
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