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6c2b374d74
Patch 3 implements the core part of PCI-Express AER and aerdrv port service driver. When a root port service device is probed, the aerdrv will call request_irq to register irq handler for AER error interrupt. When a device sends an PCI-Express error message to the root port, the root port will trigger an interrupt, by either MSI or IO-APIC, then kernel would run the irq handler. The handler collects root error status register and schedules a work. The work will call the core part to process the error based on its type (Correctable/non-fatal/fatal). As for Correctable errors, the patch chooses to just clear the correctable error status register of the device. As for the non-fatal error, the patch follows generic PCI error handler rules to call the error callback functions of the endpoint's driver. If the device is a bridge, the patch chooses to broadcast the error to downstream devices. As for the fatal error, the patch resets the pci-express link and follows generic PCI error handler rules to call the error callback functions of the endpoint's driver. If the device is a bridge, the patch chooses to broadcast the error to downstream devices. Signed-off-by: Zhang Yanmin <yanmin.zhang@intel.com> Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
81 lines
2.5 KiB
C
81 lines
2.5 KiB
C
/*
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* File: pcieport_if.h
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* Purpose: PCI Express Port Bus Driver's IF Data Structure
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*
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* Copyright (C) 2004 Intel
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* Copyright (C) Tom Long Nguyen (tom.l.nguyen@intel.com)
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*/
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#ifndef _PCIEPORT_IF_H_
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#define _PCIEPORT_IF_H_
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/* Port Type */
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#define PCIE_RC_PORT 4 /* Root port of RC */
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#define PCIE_SW_UPSTREAM_PORT 5 /* Upstream port of Switch */
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#define PCIE_SW_DOWNSTREAM_PORT 6 /* Downstream port of Switch */
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#define PCIE_ANY_PORT 7
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/* Service Type */
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#define PCIE_PORT_SERVICE_PME 1 /* Power Management Event */
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#define PCIE_PORT_SERVICE_AER 2 /* Advanced Error Reporting */
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#define PCIE_PORT_SERVICE_HP 4 /* Native Hotplug */
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#define PCIE_PORT_SERVICE_VC 8 /* Virtual Channel */
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/* Root/Upstream/Downstream Port's Interrupt Mode */
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#define PCIE_PORT_INTx_MODE 0
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#define PCIE_PORT_MSI_MODE 1
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#define PCIE_PORT_MSIX_MODE 2
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struct pcie_port_service_id {
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__u32 vendor, device; /* Vendor and device ID or PCI_ANY_ID*/
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__u32 subvendor, subdevice; /* Subsystem ID's or PCI_ANY_ID */
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__u32 class, class_mask; /* (class,subclass,prog-if) triplet */
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__u32 port_type, service_type; /* Port Entity */
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kernel_ulong_t driver_data;
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};
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struct pcie_device {
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int irq; /* Service IRQ/MSI/MSI-X Vector */
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int interrupt_mode; /* [0:INTx | 1:MSI | 2:MSI-X] */
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struct pcie_port_service_id id; /* Service ID */
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struct pci_dev *port; /* Root/Upstream/Downstream Port */
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void *priv_data; /* Service Private Data */
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struct device device; /* Generic Device Interface */
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};
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#define to_pcie_device(d) container_of(d, struct pcie_device, device)
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static inline void set_service_data(struct pcie_device *dev, void *data)
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{
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dev->priv_data = data;
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}
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static inline void* get_service_data(struct pcie_device *dev)
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{
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return dev->priv_data;
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}
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struct pcie_port_service_driver {
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const char *name;
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int (*probe) (struct pcie_device *dev,
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const struct pcie_port_service_id *id);
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void (*remove) (struct pcie_device *dev);
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int (*suspend) (struct pcie_device *dev, pm_message_t state);
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int (*resume) (struct pcie_device *dev);
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/* Service Error Recovery Handler */
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struct pci_error_handlers *err_handler;
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/* Link Reset Capability - AER service driver specific */
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pci_ers_result_t (*reset_link) (struct pci_dev *dev);
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const struct pcie_port_service_id *id_table;
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struct device_driver driver;
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};
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#define to_service_driver(d) \
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container_of(d, struct pcie_port_service_driver, driver)
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extern int pcie_port_service_register(struct pcie_port_service_driver *new);
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extern void pcie_port_service_unregister(struct pcie_port_service_driver *new);
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#endif /* _PCIEPORT_IF_H_ */
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