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e8c331e963
Some ACPI related PCI hotplug code can be shared among PCI hotplug drivers. This patch introduces the following functions in drivers/pci/hotplug/acpi_pcihp.c to share the code, and changes acpiphp and pciehp to use them. - int acpi_pci_detect_ejectable(struct pci_bus *pbus) This checks if the specified PCI bus has ejectable slots. - int acpi_pci_check_ejectable(struct pci_bus *pbus, acpi_handle handle) This checks if the specified handle is ejectable ACPI PCI slot. The 'pbus' parameter is needed to check if 'handle' is PCI related ACPI object. This patch also introduces the following inline function in include/linux/pci-acpi.h, which is useful to get ACPI handle of the PCI bridge from struct pci_bus of the bridge's secondary bus. - static inline acpi_handle acpi_pci_get_bridge_handle(struct pci_bus *pbus) This returns ACPI handle of the PCI bridge which generates PCI bus specified by 'pbus'. Signed-off-by: Kenji Kaneshige <kaneshige.kenji@jp.fujitsu.com> Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
84 lines
2.2 KiB
C
84 lines
2.2 KiB
C
/*
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* File pci-acpi.h
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*
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* Copyright (C) 2004 Intel
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* Copyright (C) Tom Long Nguyen (tom.l.nguyen@intel.com)
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*/
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#ifndef _PCI_ACPI_H_
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#define _PCI_ACPI_H_
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#include <linux/acpi.h>
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#define OSC_QUERY_TYPE 0
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#define OSC_SUPPORT_TYPE 1
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#define OSC_CONTROL_TYPE 2
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#define OSC_SUPPORT_MASKS 0x1f
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/*
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* _OSC DW0 Definition
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*/
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#define OSC_QUERY_ENABLE 1
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#define OSC_REQUEST_ERROR 2
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#define OSC_INVALID_UUID_ERROR 4
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#define OSC_INVALID_REVISION_ERROR 8
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#define OSC_CAPABILITIES_MASK_ERROR 16
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/*
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* _OSC DW1 Definition (OS Support Fields)
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*/
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#define OSC_EXT_PCI_CONFIG_SUPPORT 1
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#define OSC_ACTIVE_STATE_PWR_SUPPORT 2
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#define OSC_CLOCK_PWR_CAPABILITY_SUPPORT 4
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#define OSC_PCI_SEGMENT_GROUPS_SUPPORT 8
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#define OSC_MSI_SUPPORT 16
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/*
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* _OSC DW1 Definition (OS Control Fields)
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*/
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#define OSC_PCI_EXPRESS_NATIVE_HP_CONTROL 1
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#define OSC_SHPC_NATIVE_HP_CONTROL 2
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#define OSC_PCI_EXPRESS_PME_CONTROL 4
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#define OSC_PCI_EXPRESS_AER_CONTROL 8
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#define OSC_PCI_EXPRESS_CAP_STRUCTURE_CONTROL 16
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#define OSC_CONTROL_MASKS (OSC_PCI_EXPRESS_NATIVE_HP_CONTROL | \
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OSC_SHPC_NATIVE_HP_CONTROL | \
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OSC_PCI_EXPRESS_PME_CONTROL | \
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OSC_PCI_EXPRESS_AER_CONTROL | \
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OSC_PCI_EXPRESS_CAP_STRUCTURE_CONTROL)
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#ifdef CONFIG_ACPI
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extern acpi_status pci_osc_control_set(acpi_handle handle, u32 flags);
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int pci_acpi_osc_support(acpi_handle handle, u32 flags);
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static inline acpi_handle acpi_find_root_bridge_handle(struct pci_dev *pdev)
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{
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/* Find root host bridge */
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while (pdev->bus->self)
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pdev = pdev->bus->self;
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return acpi_get_pci_rootbridge_handle(pci_domain_nr(pdev->bus),
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pdev->bus->number);
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}
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static inline acpi_handle acpi_pci_get_bridge_handle(struct pci_bus *pbus)
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{
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int seg = pci_domain_nr(pbus), busnr = pbus->number;
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struct pci_dev *bridge = pbus->self;
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if (bridge)
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return DEVICE_ACPI_HANDLE(&(bridge->dev));
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return acpi_get_pci_rootbridge_handle(seg, busnr);
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}
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#else
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#if !defined(AE_ERROR)
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typedef u32 acpi_status;
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#define AE_ERROR (acpi_status) (0x0001)
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#endif
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static inline acpi_status pci_osc_control_set(acpi_handle handle, u32 flags)
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{return AE_ERROR;}
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static inline acpi_handle acpi_find_root_bridge_handle(struct pci_dev *pdev)
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{ return NULL; }
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#endif
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#endif /* _PCI_ACPI_H_ */
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