mirror of
https://github.com/edk2-porting/linux-next.git
synced 2024-12-27 14:43:58 +08:00
34027ca2bb
The pin id for a given tuple listed in a fsl,pins property is calculated
by dividing the first entry (which is also a register offset) by 4.
As the first available register is at offset 0x8 and configures the pad
MX25_PAD_A10 the right id for this pin is 2. All other pins are off by
one, too.
This patch drops the definition MX25_PAD_RESERVE1 (together with its
only use) and decrements all following values by 1.
Fixes: b4a87c9b96 ("pinctrl: pinctrl-imx: add imx25 pinctrl driver")
Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
Tested-by: Fabio Estevam <fabio.estevam@freescale.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
349 lines
9.6 KiB
C
349 lines
9.6 KiB
C
/*
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* imx25 pinctrl driver.
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*
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* Copyright 2013 Eukréa Electromatique <denis@eukrea.com>
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*
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* This driver was mostly copied from the imx51 pinctrl driver which has:
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*
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* Copyright (C) 2012 Freescale Semiconductor, Inc.
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* Copyright (C) 2012 Linaro, Inc.
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*
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* Author: Denis Carikli <denis@eukrea.com>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as published
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* by the Free Software Foundation.
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*/
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#include <linux/err.h>
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#include <linux/init.h>
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#include <linux/io.h>
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#include <linux/module.h>
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#include <linux/of.h>
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#include <linux/of_device.h>
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#include <linux/pinctrl/pinctrl.h>
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#include "pinctrl-imx.h"
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enum imx25_pads {
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MX25_PAD_RESERVE0 = 1,
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MX25_PAD_A10 = 2,
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MX25_PAD_A13 = 3,
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MX25_PAD_A14 = 4,
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MX25_PAD_A15 = 5,
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MX25_PAD_A16 = 6,
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MX25_PAD_A17 = 7,
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MX25_PAD_A18 = 8,
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MX25_PAD_A19 = 9,
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MX25_PAD_A20 = 10,
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MX25_PAD_A21 = 11,
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MX25_PAD_A22 = 12,
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MX25_PAD_A23 = 13,
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MX25_PAD_A24 = 14,
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MX25_PAD_A25 = 15,
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MX25_PAD_EB0 = 16,
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MX25_PAD_EB1 = 17,
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MX25_PAD_OE = 18,
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MX25_PAD_CS0 = 19,
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MX25_PAD_CS1 = 20,
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MX25_PAD_CS4 = 21,
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MX25_PAD_CS5 = 22,
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MX25_PAD_NF_CE0 = 23,
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MX25_PAD_ECB = 24,
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MX25_PAD_LBA = 25,
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MX25_PAD_BCLK = 26,
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MX25_PAD_RW = 27,
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MX25_PAD_NFWE_B = 28,
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MX25_PAD_NFRE_B = 29,
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MX25_PAD_NFALE = 30,
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MX25_PAD_NFCLE = 31,
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MX25_PAD_NFWP_B = 32,
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MX25_PAD_NFRB = 33,
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MX25_PAD_D15 = 34,
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MX25_PAD_D14 = 35,
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MX25_PAD_D13 = 36,
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MX25_PAD_D12 = 37,
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MX25_PAD_D11 = 38,
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MX25_PAD_D10 = 39,
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MX25_PAD_D9 = 40,
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MX25_PAD_D8 = 41,
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MX25_PAD_D7 = 42,
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MX25_PAD_D6 = 43,
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MX25_PAD_D5 = 44,
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MX25_PAD_D4 = 45,
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MX25_PAD_D3 = 46,
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MX25_PAD_D2 = 47,
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MX25_PAD_D1 = 48,
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MX25_PAD_D0 = 49,
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MX25_PAD_LD0 = 50,
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MX25_PAD_LD1 = 51,
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MX25_PAD_LD2 = 52,
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MX25_PAD_LD3 = 53,
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MX25_PAD_LD4 = 54,
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MX25_PAD_LD5 = 55,
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MX25_PAD_LD6 = 56,
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MX25_PAD_LD7 = 57,
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MX25_PAD_LD8 = 58,
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MX25_PAD_LD9 = 59,
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MX25_PAD_LD10 = 60,
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MX25_PAD_LD11 = 61,
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MX25_PAD_LD12 = 62,
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MX25_PAD_LD13 = 63,
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MX25_PAD_LD14 = 64,
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MX25_PAD_LD15 = 65,
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MX25_PAD_HSYNC = 66,
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MX25_PAD_VSYNC = 67,
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MX25_PAD_LSCLK = 68,
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MX25_PAD_OE_ACD = 69,
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MX25_PAD_CONTRAST = 70,
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MX25_PAD_PWM = 71,
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MX25_PAD_CSI_D2 = 72,
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MX25_PAD_CSI_D3 = 73,
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MX25_PAD_CSI_D4 = 74,
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MX25_PAD_CSI_D5 = 75,
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MX25_PAD_CSI_D6 = 76,
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MX25_PAD_CSI_D7 = 77,
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MX25_PAD_CSI_D8 = 78,
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MX25_PAD_CSI_D9 = 79,
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MX25_PAD_CSI_MCLK = 80,
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MX25_PAD_CSI_VSYNC = 81,
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MX25_PAD_CSI_HSYNC = 82,
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MX25_PAD_CSI_PIXCLK = 83,
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MX25_PAD_I2C1_CLK = 84,
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MX25_PAD_I2C1_DAT = 85,
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MX25_PAD_CSPI1_MOSI = 86,
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MX25_PAD_CSPI1_MISO = 87,
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MX25_PAD_CSPI1_SS0 = 88,
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MX25_PAD_CSPI1_SS1 = 89,
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MX25_PAD_CSPI1_SCLK = 90,
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MX25_PAD_CSPI1_RDY = 91,
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MX25_PAD_UART1_RXD = 92,
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MX25_PAD_UART1_TXD = 93,
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MX25_PAD_UART1_RTS = 94,
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MX25_PAD_UART1_CTS = 95,
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MX25_PAD_UART2_RXD = 96,
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MX25_PAD_UART2_TXD = 97,
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MX25_PAD_UART2_RTS = 98,
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MX25_PAD_UART2_CTS = 99,
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MX25_PAD_SD1_CMD = 100,
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MX25_PAD_SD1_CLK = 101,
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MX25_PAD_SD1_DATA0 = 102,
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MX25_PAD_SD1_DATA1 = 103,
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MX25_PAD_SD1_DATA2 = 104,
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MX25_PAD_SD1_DATA3 = 105,
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MX25_PAD_KPP_ROW0 = 106,
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MX25_PAD_KPP_ROW1 = 107,
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MX25_PAD_KPP_ROW2 = 108,
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MX25_PAD_KPP_ROW3 = 109,
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MX25_PAD_KPP_COL0 = 110,
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MX25_PAD_KPP_COL1 = 111,
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MX25_PAD_KPP_COL2 = 112,
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MX25_PAD_KPP_COL3 = 113,
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MX25_PAD_FEC_MDC = 114,
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MX25_PAD_FEC_MDIO = 115,
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MX25_PAD_FEC_TDATA0 = 116,
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MX25_PAD_FEC_TDATA1 = 117,
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MX25_PAD_FEC_TX_EN = 118,
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MX25_PAD_FEC_RDATA0 = 119,
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MX25_PAD_FEC_RDATA1 = 120,
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MX25_PAD_FEC_RX_DV = 121,
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MX25_PAD_FEC_TX_CLK = 122,
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MX25_PAD_RTCK = 123,
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MX25_PAD_DE_B = 124,
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MX25_PAD_GPIO_A = 125,
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MX25_PAD_GPIO_B = 126,
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MX25_PAD_GPIO_C = 127,
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MX25_PAD_GPIO_D = 128,
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MX25_PAD_GPIO_E = 129,
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MX25_PAD_GPIO_F = 130,
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MX25_PAD_EXT_ARMCLK = 131,
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MX25_PAD_UPLL_BYPCLK = 132,
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MX25_PAD_VSTBY_REQ = 133,
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MX25_PAD_VSTBY_ACK = 134,
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MX25_PAD_POWER_FAIL = 135,
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MX25_PAD_CLKO = 136,
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MX25_PAD_BOOT_MODE0 = 137,
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MX25_PAD_BOOT_MODE1 = 138,
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};
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/* Pad names for the pinmux subsystem */
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static const struct pinctrl_pin_desc imx25_pinctrl_pads[] = {
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IMX_PINCTRL_PIN(MX25_PAD_RESERVE0),
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IMX_PINCTRL_PIN(MX25_PAD_A10),
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IMX_PINCTRL_PIN(MX25_PAD_A13),
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IMX_PINCTRL_PIN(MX25_PAD_A14),
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IMX_PINCTRL_PIN(MX25_PAD_A15),
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IMX_PINCTRL_PIN(MX25_PAD_A16),
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IMX_PINCTRL_PIN(MX25_PAD_A17),
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IMX_PINCTRL_PIN(MX25_PAD_A18),
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IMX_PINCTRL_PIN(MX25_PAD_A19),
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IMX_PINCTRL_PIN(MX25_PAD_A20),
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IMX_PINCTRL_PIN(MX25_PAD_A21),
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IMX_PINCTRL_PIN(MX25_PAD_A22),
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IMX_PINCTRL_PIN(MX25_PAD_A23),
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IMX_PINCTRL_PIN(MX25_PAD_A24),
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IMX_PINCTRL_PIN(MX25_PAD_A25),
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IMX_PINCTRL_PIN(MX25_PAD_EB0),
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IMX_PINCTRL_PIN(MX25_PAD_EB1),
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IMX_PINCTRL_PIN(MX25_PAD_OE),
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IMX_PINCTRL_PIN(MX25_PAD_CS0),
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IMX_PINCTRL_PIN(MX25_PAD_CS1),
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IMX_PINCTRL_PIN(MX25_PAD_CS4),
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IMX_PINCTRL_PIN(MX25_PAD_CS5),
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IMX_PINCTRL_PIN(MX25_PAD_NF_CE0),
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IMX_PINCTRL_PIN(MX25_PAD_ECB),
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IMX_PINCTRL_PIN(MX25_PAD_LBA),
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IMX_PINCTRL_PIN(MX25_PAD_BCLK),
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IMX_PINCTRL_PIN(MX25_PAD_RW),
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IMX_PINCTRL_PIN(MX25_PAD_NFWE_B),
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IMX_PINCTRL_PIN(MX25_PAD_NFRE_B),
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IMX_PINCTRL_PIN(MX25_PAD_NFALE),
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IMX_PINCTRL_PIN(MX25_PAD_NFCLE),
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IMX_PINCTRL_PIN(MX25_PAD_NFWP_B),
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IMX_PINCTRL_PIN(MX25_PAD_NFRB),
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IMX_PINCTRL_PIN(MX25_PAD_D15),
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IMX_PINCTRL_PIN(MX25_PAD_D14),
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IMX_PINCTRL_PIN(MX25_PAD_D13),
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IMX_PINCTRL_PIN(MX25_PAD_D12),
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IMX_PINCTRL_PIN(MX25_PAD_D11),
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IMX_PINCTRL_PIN(MX25_PAD_D10),
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IMX_PINCTRL_PIN(MX25_PAD_D9),
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IMX_PINCTRL_PIN(MX25_PAD_D8),
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IMX_PINCTRL_PIN(MX25_PAD_D7),
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IMX_PINCTRL_PIN(MX25_PAD_D6),
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IMX_PINCTRL_PIN(MX25_PAD_D5),
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IMX_PINCTRL_PIN(MX25_PAD_D4),
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IMX_PINCTRL_PIN(MX25_PAD_D3),
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IMX_PINCTRL_PIN(MX25_PAD_D2),
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IMX_PINCTRL_PIN(MX25_PAD_D1),
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IMX_PINCTRL_PIN(MX25_PAD_D0),
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IMX_PINCTRL_PIN(MX25_PAD_LD0),
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IMX_PINCTRL_PIN(MX25_PAD_LD1),
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IMX_PINCTRL_PIN(MX25_PAD_LD2),
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IMX_PINCTRL_PIN(MX25_PAD_LD3),
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IMX_PINCTRL_PIN(MX25_PAD_LD4),
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IMX_PINCTRL_PIN(MX25_PAD_LD5),
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IMX_PINCTRL_PIN(MX25_PAD_LD6),
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IMX_PINCTRL_PIN(MX25_PAD_LD7),
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IMX_PINCTRL_PIN(MX25_PAD_LD8),
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IMX_PINCTRL_PIN(MX25_PAD_LD9),
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IMX_PINCTRL_PIN(MX25_PAD_LD10),
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IMX_PINCTRL_PIN(MX25_PAD_LD11),
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IMX_PINCTRL_PIN(MX25_PAD_LD12),
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IMX_PINCTRL_PIN(MX25_PAD_LD13),
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IMX_PINCTRL_PIN(MX25_PAD_LD14),
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IMX_PINCTRL_PIN(MX25_PAD_LD15),
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IMX_PINCTRL_PIN(MX25_PAD_HSYNC),
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IMX_PINCTRL_PIN(MX25_PAD_VSYNC),
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IMX_PINCTRL_PIN(MX25_PAD_LSCLK),
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IMX_PINCTRL_PIN(MX25_PAD_OE_ACD),
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IMX_PINCTRL_PIN(MX25_PAD_CONTRAST),
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IMX_PINCTRL_PIN(MX25_PAD_PWM),
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IMX_PINCTRL_PIN(MX25_PAD_CSI_D2),
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IMX_PINCTRL_PIN(MX25_PAD_CSI_D3),
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IMX_PINCTRL_PIN(MX25_PAD_CSI_D4),
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IMX_PINCTRL_PIN(MX25_PAD_CSI_D5),
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IMX_PINCTRL_PIN(MX25_PAD_CSI_D6),
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IMX_PINCTRL_PIN(MX25_PAD_CSI_D7),
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IMX_PINCTRL_PIN(MX25_PAD_CSI_D8),
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IMX_PINCTRL_PIN(MX25_PAD_CSI_D9),
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IMX_PINCTRL_PIN(MX25_PAD_CSI_MCLK),
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IMX_PINCTRL_PIN(MX25_PAD_CSI_VSYNC),
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IMX_PINCTRL_PIN(MX25_PAD_CSI_HSYNC),
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IMX_PINCTRL_PIN(MX25_PAD_CSI_PIXCLK),
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IMX_PINCTRL_PIN(MX25_PAD_I2C1_CLK),
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IMX_PINCTRL_PIN(MX25_PAD_I2C1_DAT),
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IMX_PINCTRL_PIN(MX25_PAD_CSPI1_MOSI),
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IMX_PINCTRL_PIN(MX25_PAD_CSPI1_MISO),
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IMX_PINCTRL_PIN(MX25_PAD_CSPI1_SS0),
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IMX_PINCTRL_PIN(MX25_PAD_CSPI1_SS1),
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IMX_PINCTRL_PIN(MX25_PAD_CSPI1_SCLK),
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IMX_PINCTRL_PIN(MX25_PAD_CSPI1_RDY),
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IMX_PINCTRL_PIN(MX25_PAD_UART1_RXD),
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IMX_PINCTRL_PIN(MX25_PAD_UART1_TXD),
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IMX_PINCTRL_PIN(MX25_PAD_UART1_RTS),
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IMX_PINCTRL_PIN(MX25_PAD_UART1_CTS),
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IMX_PINCTRL_PIN(MX25_PAD_UART2_RXD),
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IMX_PINCTRL_PIN(MX25_PAD_UART2_TXD),
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IMX_PINCTRL_PIN(MX25_PAD_UART2_RTS),
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IMX_PINCTRL_PIN(MX25_PAD_UART2_CTS),
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IMX_PINCTRL_PIN(MX25_PAD_SD1_CMD),
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IMX_PINCTRL_PIN(MX25_PAD_SD1_CLK),
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IMX_PINCTRL_PIN(MX25_PAD_SD1_DATA0),
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IMX_PINCTRL_PIN(MX25_PAD_SD1_DATA1),
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IMX_PINCTRL_PIN(MX25_PAD_SD1_DATA2),
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IMX_PINCTRL_PIN(MX25_PAD_SD1_DATA3),
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IMX_PINCTRL_PIN(MX25_PAD_KPP_ROW0),
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IMX_PINCTRL_PIN(MX25_PAD_KPP_ROW1),
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IMX_PINCTRL_PIN(MX25_PAD_KPP_ROW2),
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IMX_PINCTRL_PIN(MX25_PAD_KPP_ROW3),
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IMX_PINCTRL_PIN(MX25_PAD_KPP_COL0),
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IMX_PINCTRL_PIN(MX25_PAD_KPP_COL1),
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IMX_PINCTRL_PIN(MX25_PAD_KPP_COL2),
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IMX_PINCTRL_PIN(MX25_PAD_KPP_COL3),
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IMX_PINCTRL_PIN(MX25_PAD_FEC_MDC),
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IMX_PINCTRL_PIN(MX25_PAD_FEC_MDIO),
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IMX_PINCTRL_PIN(MX25_PAD_FEC_TDATA0),
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IMX_PINCTRL_PIN(MX25_PAD_FEC_TDATA1),
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IMX_PINCTRL_PIN(MX25_PAD_FEC_TX_EN),
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IMX_PINCTRL_PIN(MX25_PAD_FEC_RDATA0),
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IMX_PINCTRL_PIN(MX25_PAD_FEC_RDATA1),
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IMX_PINCTRL_PIN(MX25_PAD_FEC_RX_DV),
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IMX_PINCTRL_PIN(MX25_PAD_FEC_TX_CLK),
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IMX_PINCTRL_PIN(MX25_PAD_RTCK),
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IMX_PINCTRL_PIN(MX25_PAD_DE_B),
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IMX_PINCTRL_PIN(MX25_PAD_GPIO_A),
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IMX_PINCTRL_PIN(MX25_PAD_GPIO_B),
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IMX_PINCTRL_PIN(MX25_PAD_GPIO_C),
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IMX_PINCTRL_PIN(MX25_PAD_GPIO_D),
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IMX_PINCTRL_PIN(MX25_PAD_GPIO_E),
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IMX_PINCTRL_PIN(MX25_PAD_GPIO_F),
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IMX_PINCTRL_PIN(MX25_PAD_EXT_ARMCLK),
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IMX_PINCTRL_PIN(MX25_PAD_UPLL_BYPCLK),
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IMX_PINCTRL_PIN(MX25_PAD_VSTBY_REQ),
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IMX_PINCTRL_PIN(MX25_PAD_VSTBY_ACK),
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IMX_PINCTRL_PIN(MX25_PAD_POWER_FAIL),
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IMX_PINCTRL_PIN(MX25_PAD_CLKO),
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IMX_PINCTRL_PIN(MX25_PAD_BOOT_MODE0),
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IMX_PINCTRL_PIN(MX25_PAD_BOOT_MODE1),
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};
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static struct imx_pinctrl_soc_info imx25_pinctrl_info = {
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.pins = imx25_pinctrl_pads,
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.npins = ARRAY_SIZE(imx25_pinctrl_pads),
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};
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static const struct of_device_id imx25_pinctrl_of_match[] = {
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{ .compatible = "fsl,imx25-iomuxc", },
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{ /* sentinel */ }
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};
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static int imx25_pinctrl_probe(struct platform_device *pdev)
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{
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return imx_pinctrl_probe(pdev, &imx25_pinctrl_info);
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}
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static struct platform_driver imx25_pinctrl_driver = {
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.driver = {
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.name = "imx25-pinctrl",
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.of_match_table = of_match_ptr(imx25_pinctrl_of_match),
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},
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.probe = imx25_pinctrl_probe,
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.remove = imx_pinctrl_remove,
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};
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static int __init imx25_pinctrl_init(void)
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{
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return platform_driver_register(&imx25_pinctrl_driver);
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}
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arch_initcall(imx25_pinctrl_init);
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static void __exit imx25_pinctrl_exit(void)
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{
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platform_driver_unregister(&imx25_pinctrl_driver);
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}
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module_exit(imx25_pinctrl_exit);
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MODULE_AUTHOR("Denis Carikli <denis@eukrea.com>");
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MODULE_DESCRIPTION("Freescale IMX25 pinctrl driver");
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MODULE_LICENSE("GPL v2");
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