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389eda15e0
Support clk in gpio driver. There's no gpio clock in PXA25x and PXA27x. So use dummy clk instead. And move the gpio edge initialization into gpio driver for arch-mmp. Signed-off-by: Haojian Zhuang <haojian.zhuang@marvell.com>
616 lines
15 KiB
C
616 lines
15 KiB
C
/*
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* linux/arch/arm/plat-pxa/gpio.c
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*
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* Generic PXA GPIO handling
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*
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* Author: Nicolas Pitre
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* Created: Jun 15, 2001
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* Copyright: MontaVista Software Inc.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#include <linux/clk.h>
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#include <linux/err.h>
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#include <linux/gpio.h>
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#include <linux/gpio-pxa.h>
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#include <linux/init.h>
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#include <linux/irq.h>
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#include <linux/io.h>
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#include <linux/platform_device.h>
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#include <linux/syscore_ops.h>
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#include <linux/slab.h>
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/*
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* We handle the GPIOs by banks, each bank covers up to 32 GPIOs with
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* one set of registers. The register offsets are organized below:
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*
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* GPLR GPDR GPSR GPCR GRER GFER GEDR
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* BANK 0 - 0x0000 0x000C 0x0018 0x0024 0x0030 0x003C 0x0048
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* BANK 1 - 0x0004 0x0010 0x001C 0x0028 0x0034 0x0040 0x004C
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* BANK 2 - 0x0008 0x0014 0x0020 0x002C 0x0038 0x0044 0x0050
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*
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* BANK 3 - 0x0100 0x010C 0x0118 0x0124 0x0130 0x013C 0x0148
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* BANK 4 - 0x0104 0x0110 0x011C 0x0128 0x0134 0x0140 0x014C
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* BANK 5 - 0x0108 0x0114 0x0120 0x012C 0x0138 0x0144 0x0150
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*
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* NOTE:
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* BANK 3 is only available on PXA27x and later processors.
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* BANK 4 and 5 are only available on PXA935
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*/
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#define GPLR_OFFSET 0x00
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#define GPDR_OFFSET 0x0C
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#define GPSR_OFFSET 0x18
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#define GPCR_OFFSET 0x24
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#define GRER_OFFSET 0x30
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#define GFER_OFFSET 0x3C
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#define GEDR_OFFSET 0x48
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#define GAFR_OFFSET 0x54
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#define ED_MASK_OFFSET 0x9C /* GPIO edge detection for AP side */
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#define BANK_OFF(n) (((n) < 3) ? (n) << 2 : 0x100 + (((n) - 3) << 2))
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int pxa_last_gpio;
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struct pxa_gpio_chip {
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struct gpio_chip chip;
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void __iomem *regbase;
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char label[10];
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unsigned long irq_mask;
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unsigned long irq_edge_rise;
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unsigned long irq_edge_fall;
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#ifdef CONFIG_PM
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unsigned long saved_gplr;
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unsigned long saved_gpdr;
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unsigned long saved_grer;
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unsigned long saved_gfer;
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#endif
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};
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enum {
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PXA25X_GPIO = 0,
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PXA26X_GPIO,
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PXA27X_GPIO,
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PXA3XX_GPIO,
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PXA93X_GPIO,
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MMP_GPIO = 0x10,
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MMP2_GPIO,
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};
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static DEFINE_SPINLOCK(gpio_lock);
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static struct pxa_gpio_chip *pxa_gpio_chips;
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static int gpio_type;
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static void __iomem *gpio_reg_base;
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#define for_each_gpio_chip(i, c) \
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for (i = 0, c = &pxa_gpio_chips[0]; i <= pxa_last_gpio; i += 32, c++)
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static inline void __iomem *gpio_chip_base(struct gpio_chip *c)
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{
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return container_of(c, struct pxa_gpio_chip, chip)->regbase;
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}
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static inline struct pxa_gpio_chip *gpio_to_pxachip(unsigned gpio)
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{
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return &pxa_gpio_chips[gpio_to_bank(gpio)];
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}
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static inline int gpio_is_pxa_type(int type)
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{
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return (type & MMP_GPIO) == 0;
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}
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static inline int gpio_is_mmp_type(int type)
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{
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return (type & MMP_GPIO) != 0;
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}
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/* GPIO86/87/88/89 on PXA26x have their direction bits in PXA_GPDR(2 inverted,
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* as well as their Alternate Function value being '1' for GPIO in GAFRx.
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*/
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static inline int __gpio_is_inverted(int gpio)
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{
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if ((gpio_type == PXA26X_GPIO) && (gpio > 85))
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return 1;
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return 0;
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}
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/*
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* On PXA25x and PXA27x, GAFRx and GPDRx together decide the alternate
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* function of a GPIO, and GPDRx cannot be altered once configured. It
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* is attributed as "occupied" here (I know this terminology isn't
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* accurate, you are welcome to propose a better one :-)
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*/
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static inline int __gpio_is_occupied(unsigned gpio)
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{
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struct pxa_gpio_chip *pxachip;
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void __iomem *base;
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unsigned long gafr = 0, gpdr = 0;
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int ret, af = 0, dir = 0;
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pxachip = gpio_to_pxachip(gpio);
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base = gpio_chip_base(&pxachip->chip);
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gpdr = readl_relaxed(base + GPDR_OFFSET);
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switch (gpio_type) {
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case PXA25X_GPIO:
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case PXA26X_GPIO:
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case PXA27X_GPIO:
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gafr = readl_relaxed(base + GAFR_OFFSET);
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af = (gafr >> ((gpio & 0xf) * 2)) & 0x3;
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dir = gpdr & GPIO_bit(gpio);
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if (__gpio_is_inverted(gpio))
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ret = (af != 1) || (dir == 0);
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else
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ret = (af != 0) || (dir != 0);
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break;
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default:
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ret = gpdr & GPIO_bit(gpio);
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break;
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}
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return ret;
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}
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#ifdef CONFIG_ARCH_PXA
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static inline int __pxa_gpio_to_irq(int gpio)
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{
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if (gpio_is_pxa_type(gpio_type))
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return PXA_GPIO_TO_IRQ(gpio);
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return -1;
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}
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static inline int __pxa_irq_to_gpio(int irq)
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{
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if (gpio_is_pxa_type(gpio_type))
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return irq - PXA_GPIO_TO_IRQ(0);
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return -1;
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}
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#else
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static inline int __pxa_gpio_to_irq(int gpio) { return -1; }
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static inline int __pxa_irq_to_gpio(int irq) { return -1; }
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#endif
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#ifdef CONFIG_ARCH_MMP
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static inline int __mmp_gpio_to_irq(int gpio)
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{
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if (gpio_is_mmp_type(gpio_type))
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return MMP_GPIO_TO_IRQ(gpio);
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return -1;
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}
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static inline int __mmp_irq_to_gpio(int irq)
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{
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if (gpio_is_mmp_type(gpio_type))
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return irq - MMP_GPIO_TO_IRQ(0);
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return -1;
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}
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#else
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static inline int __mmp_gpio_to_irq(int gpio) { return -1; }
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static inline int __mmp_irq_to_gpio(int irq) { return -1; }
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#endif
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static int pxa_gpio_to_irq(struct gpio_chip *chip, unsigned offset)
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{
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int gpio, ret;
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gpio = chip->base + offset;
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ret = __pxa_gpio_to_irq(gpio);
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if (ret >= 0)
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return ret;
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return __mmp_gpio_to_irq(gpio);
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}
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int pxa_irq_to_gpio(int irq)
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{
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int ret;
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ret = __pxa_irq_to_gpio(irq);
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if (ret >= 0)
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return ret;
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return __mmp_irq_to_gpio(irq);
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}
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static int pxa_gpio_direction_input(struct gpio_chip *chip, unsigned offset)
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{
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void __iomem *base = gpio_chip_base(chip);
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uint32_t value, mask = 1 << offset;
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unsigned long flags;
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spin_lock_irqsave(&gpio_lock, flags);
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value = readl_relaxed(base + GPDR_OFFSET);
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if (__gpio_is_inverted(chip->base + offset))
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value |= mask;
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else
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value &= ~mask;
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writel_relaxed(value, base + GPDR_OFFSET);
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spin_unlock_irqrestore(&gpio_lock, flags);
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return 0;
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}
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static int pxa_gpio_direction_output(struct gpio_chip *chip,
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unsigned offset, int value)
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{
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void __iomem *base = gpio_chip_base(chip);
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uint32_t tmp, mask = 1 << offset;
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unsigned long flags;
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writel_relaxed(mask, base + (value ? GPSR_OFFSET : GPCR_OFFSET));
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spin_lock_irqsave(&gpio_lock, flags);
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tmp = readl_relaxed(base + GPDR_OFFSET);
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if (__gpio_is_inverted(chip->base + offset))
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tmp &= ~mask;
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else
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tmp |= mask;
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writel_relaxed(tmp, base + GPDR_OFFSET);
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spin_unlock_irqrestore(&gpio_lock, flags);
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return 0;
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}
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static int pxa_gpio_get(struct gpio_chip *chip, unsigned offset)
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{
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return readl_relaxed(gpio_chip_base(chip) + GPLR_OFFSET) & (1 << offset);
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}
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static void pxa_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
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{
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writel_relaxed(1 << offset, gpio_chip_base(chip) +
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(value ? GPSR_OFFSET : GPCR_OFFSET));
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}
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static int __devinit pxa_init_gpio_chip(int gpio_end)
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{
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int i, gpio, nbanks = gpio_to_bank(gpio_end) + 1;
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struct pxa_gpio_chip *chips;
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chips = kzalloc(nbanks * sizeof(struct pxa_gpio_chip), GFP_KERNEL);
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if (chips == NULL) {
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pr_err("%s: failed to allocate GPIO chips\n", __func__);
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return -ENOMEM;
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}
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for (i = 0, gpio = 0; i < nbanks; i++, gpio += 32) {
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struct gpio_chip *c = &chips[i].chip;
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sprintf(chips[i].label, "gpio-%d", i);
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chips[i].regbase = gpio_reg_base + BANK_OFF(i);
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c->base = gpio;
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c->label = chips[i].label;
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c->direction_input = pxa_gpio_direction_input;
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c->direction_output = pxa_gpio_direction_output;
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c->get = pxa_gpio_get;
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c->set = pxa_gpio_set;
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c->to_irq = pxa_gpio_to_irq;
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/* number of GPIOs on last bank may be less than 32 */
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c->ngpio = (gpio + 31 > gpio_end) ? (gpio_end - gpio + 1) : 32;
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gpiochip_add(c);
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}
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pxa_gpio_chips = chips;
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return 0;
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}
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/* Update only those GRERx and GFERx edge detection register bits if those
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* bits are set in c->irq_mask
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*/
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static inline void update_edge_detect(struct pxa_gpio_chip *c)
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{
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uint32_t grer, gfer;
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grer = readl_relaxed(c->regbase + GRER_OFFSET) & ~c->irq_mask;
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gfer = readl_relaxed(c->regbase + GFER_OFFSET) & ~c->irq_mask;
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grer |= c->irq_edge_rise & c->irq_mask;
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gfer |= c->irq_edge_fall & c->irq_mask;
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writel_relaxed(grer, c->regbase + GRER_OFFSET);
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writel_relaxed(gfer, c->regbase + GFER_OFFSET);
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}
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static int pxa_gpio_irq_type(struct irq_data *d, unsigned int type)
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{
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struct pxa_gpio_chip *c;
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int gpio = pxa_irq_to_gpio(d->irq);
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unsigned long gpdr, mask = GPIO_bit(gpio);
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c = gpio_to_pxachip(gpio);
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if (type == IRQ_TYPE_PROBE) {
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/* Don't mess with enabled GPIOs using preconfigured edges or
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* GPIOs set to alternate function or to output during probe
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*/
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if ((c->irq_edge_rise | c->irq_edge_fall) & GPIO_bit(gpio))
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return 0;
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if (__gpio_is_occupied(gpio))
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return 0;
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type = IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING;
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}
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gpdr = readl_relaxed(c->regbase + GPDR_OFFSET);
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if (__gpio_is_inverted(gpio))
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writel_relaxed(gpdr | mask, c->regbase + GPDR_OFFSET);
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else
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writel_relaxed(gpdr & ~mask, c->regbase + GPDR_OFFSET);
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if (type & IRQ_TYPE_EDGE_RISING)
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c->irq_edge_rise |= mask;
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else
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c->irq_edge_rise &= ~mask;
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if (type & IRQ_TYPE_EDGE_FALLING)
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c->irq_edge_fall |= mask;
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else
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c->irq_edge_fall &= ~mask;
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update_edge_detect(c);
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pr_debug("%s: IRQ%d (GPIO%d) - edge%s%s\n", __func__, d->irq, gpio,
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((type & IRQ_TYPE_EDGE_RISING) ? " rising" : ""),
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((type & IRQ_TYPE_EDGE_FALLING) ? " falling" : ""));
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return 0;
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}
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static void pxa_gpio_demux_handler(unsigned int irq, struct irq_desc *desc)
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{
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struct pxa_gpio_chip *c;
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int loop, gpio, gpio_base, n;
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unsigned long gedr;
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do {
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loop = 0;
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for_each_gpio_chip(gpio, c) {
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gpio_base = c->chip.base;
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gedr = readl_relaxed(c->regbase + GEDR_OFFSET);
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gedr = gedr & c->irq_mask;
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writel_relaxed(gedr, c->regbase + GEDR_OFFSET);
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n = find_first_bit(&gedr, BITS_PER_LONG);
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while (n < BITS_PER_LONG) {
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loop = 1;
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generic_handle_irq(gpio_to_irq(gpio_base + n));
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n = find_next_bit(&gedr, BITS_PER_LONG, n + 1);
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}
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}
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} while (loop);
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}
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static void pxa_ack_muxed_gpio(struct irq_data *d)
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{
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int gpio = pxa_irq_to_gpio(d->irq);
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struct pxa_gpio_chip *c = gpio_to_pxachip(gpio);
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writel_relaxed(GPIO_bit(gpio), c->regbase + GEDR_OFFSET);
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}
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static void pxa_mask_muxed_gpio(struct irq_data *d)
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{
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int gpio = pxa_irq_to_gpio(d->irq);
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struct pxa_gpio_chip *c = gpio_to_pxachip(gpio);
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uint32_t grer, gfer;
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c->irq_mask &= ~GPIO_bit(gpio);
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grer = readl_relaxed(c->regbase + GRER_OFFSET) & ~GPIO_bit(gpio);
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gfer = readl_relaxed(c->regbase + GFER_OFFSET) & ~GPIO_bit(gpio);
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writel_relaxed(grer, c->regbase + GRER_OFFSET);
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writel_relaxed(gfer, c->regbase + GFER_OFFSET);
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}
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static void pxa_unmask_muxed_gpio(struct irq_data *d)
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{
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int gpio = pxa_irq_to_gpio(d->irq);
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struct pxa_gpio_chip *c = gpio_to_pxachip(gpio);
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c->irq_mask |= GPIO_bit(gpio);
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update_edge_detect(c);
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}
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static struct irq_chip pxa_muxed_gpio_chip = {
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.name = "GPIO",
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.irq_ack = pxa_ack_muxed_gpio,
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.irq_mask = pxa_mask_muxed_gpio,
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.irq_unmask = pxa_unmask_muxed_gpio,
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.irq_set_type = pxa_gpio_irq_type,
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};
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static int pxa_gpio_nums(void)
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{
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int count = 0;
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#ifdef CONFIG_ARCH_PXA
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if (cpu_is_pxa25x()) {
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#ifdef CONFIG_CPU_PXA26x
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count = 89;
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gpio_type = PXA26X_GPIO;
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#elif defined(CONFIG_PXA25x)
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count = 84;
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gpio_type = PXA26X_GPIO;
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#endif /* CONFIG_CPU_PXA26x */
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} else if (cpu_is_pxa27x()) {
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count = 120;
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gpio_type = PXA27X_GPIO;
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} else if (cpu_is_pxa93x() || cpu_is_pxa95x()) {
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count = 191;
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gpio_type = PXA93X_GPIO;
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} else if (cpu_is_pxa3xx()) {
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count = 127;
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gpio_type = PXA3XX_GPIO;
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}
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#endif /* CONFIG_ARCH_PXA */
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#ifdef CONFIG_ARCH_MMP
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if (cpu_is_pxa168() || cpu_is_pxa910()) {
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count = 127;
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gpio_type = MMP_GPIO;
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} else if (cpu_is_mmp2()) {
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count = 191;
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gpio_type = MMP2_GPIO;
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}
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#endif /* CONFIG_ARCH_MMP */
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return count;
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}
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static int __devinit pxa_gpio_probe(struct platform_device *pdev)
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{
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struct pxa_gpio_chip *c;
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struct resource *res;
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struct clk *clk;
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int gpio, irq, ret;
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int irq0 = 0, irq1 = 0, irq_mux, gpio_offset = 0;
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pxa_last_gpio = pxa_gpio_nums();
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if (!pxa_last_gpio)
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return -EINVAL;
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irq0 = platform_get_irq_byname(pdev, "gpio0");
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irq1 = platform_get_irq_byname(pdev, "gpio1");
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irq_mux = platform_get_irq_byname(pdev, "gpio_mux");
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if ((irq0 > 0 && irq1 <= 0) || (irq0 <= 0 && irq1 > 0)
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|| (irq_mux <= 0))
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return -EINVAL;
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res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
|
|
if (!res)
|
|
return -EINVAL;
|
|
gpio_reg_base = ioremap(res->start, resource_size(res));
|
|
if (!gpio_reg_base)
|
|
return -EINVAL;
|
|
|
|
if (irq0 > 0)
|
|
gpio_offset = 2;
|
|
|
|
clk = clk_get(&pdev->dev, NULL);
|
|
if (IS_ERR(clk)) {
|
|
dev_err(&pdev->dev, "Error %ld to get gpio clock\n",
|
|
PTR_ERR(clk));
|
|
iounmap(gpio_reg_base);
|
|
return PTR_ERR(clk);
|
|
}
|
|
ret = clk_prepare(clk);
|
|
if (ret) {
|
|
clk_put(clk);
|
|
iounmap(gpio_reg_base);
|
|
return ret;
|
|
}
|
|
ret = clk_enable(clk);
|
|
if (ret) {
|
|
clk_unprepare(clk);
|
|
clk_put(clk);
|
|
iounmap(gpio_reg_base);
|
|
return ret;
|
|
}
|
|
|
|
/* Initialize GPIO chips */
|
|
pxa_init_gpio_chip(pxa_last_gpio);
|
|
|
|
/* clear all GPIO edge detects */
|
|
for_each_gpio_chip(gpio, c) {
|
|
writel_relaxed(0, c->regbase + GFER_OFFSET);
|
|
writel_relaxed(0, c->regbase + GRER_OFFSET);
|
|
writel_relaxed(~0,c->regbase + GEDR_OFFSET);
|
|
/* unmask GPIO edge detect for AP side */
|
|
if (gpio_is_mmp_type(gpio_type))
|
|
writel_relaxed(~0, c->regbase + ED_MASK_OFFSET);
|
|
}
|
|
|
|
#ifdef CONFIG_ARCH_PXA
|
|
irq = gpio_to_irq(0);
|
|
irq_set_chip_and_handler(irq, &pxa_muxed_gpio_chip,
|
|
handle_edge_irq);
|
|
set_irq_flags(irq, IRQF_VALID | IRQF_PROBE);
|
|
irq_set_chained_handler(IRQ_GPIO0, pxa_gpio_demux_handler);
|
|
|
|
irq = gpio_to_irq(1);
|
|
irq_set_chip_and_handler(irq, &pxa_muxed_gpio_chip,
|
|
handle_edge_irq);
|
|
set_irq_flags(irq, IRQF_VALID | IRQF_PROBE);
|
|
irq_set_chained_handler(IRQ_GPIO1, pxa_gpio_demux_handler);
|
|
#endif
|
|
|
|
for (irq = gpio_to_irq(gpio_offset);
|
|
irq <= gpio_to_irq(pxa_last_gpio); irq++) {
|
|
irq_set_chip_and_handler(irq, &pxa_muxed_gpio_chip,
|
|
handle_edge_irq);
|
|
set_irq_flags(irq, IRQF_VALID | IRQF_PROBE);
|
|
}
|
|
|
|
irq_set_chained_handler(irq_mux, pxa_gpio_demux_handler);
|
|
return 0;
|
|
}
|
|
|
|
static struct platform_driver pxa_gpio_driver = {
|
|
.probe = pxa_gpio_probe,
|
|
.driver = {
|
|
.name = "pxa-gpio",
|
|
},
|
|
};
|
|
|
|
static int __init pxa_gpio_init(void)
|
|
{
|
|
return platform_driver_register(&pxa_gpio_driver);
|
|
}
|
|
postcore_initcall(pxa_gpio_init);
|
|
|
|
#ifdef CONFIG_PM
|
|
static int pxa_gpio_suspend(void)
|
|
{
|
|
struct pxa_gpio_chip *c;
|
|
int gpio;
|
|
|
|
for_each_gpio_chip(gpio, c) {
|
|
c->saved_gplr = readl_relaxed(c->regbase + GPLR_OFFSET);
|
|
c->saved_gpdr = readl_relaxed(c->regbase + GPDR_OFFSET);
|
|
c->saved_grer = readl_relaxed(c->regbase + GRER_OFFSET);
|
|
c->saved_gfer = readl_relaxed(c->regbase + GFER_OFFSET);
|
|
|
|
/* Clear GPIO transition detect bits */
|
|
writel_relaxed(0xffffffff, c->regbase + GEDR_OFFSET);
|
|
}
|
|
return 0;
|
|
}
|
|
|
|
static void pxa_gpio_resume(void)
|
|
{
|
|
struct pxa_gpio_chip *c;
|
|
int gpio;
|
|
|
|
for_each_gpio_chip(gpio, c) {
|
|
/* restore level with set/clear */
|
|
writel_relaxed( c->saved_gplr, c->regbase + GPSR_OFFSET);
|
|
writel_relaxed(~c->saved_gplr, c->regbase + GPCR_OFFSET);
|
|
|
|
writel_relaxed(c->saved_grer, c->regbase + GRER_OFFSET);
|
|
writel_relaxed(c->saved_gfer, c->regbase + GFER_OFFSET);
|
|
writel_relaxed(c->saved_gpdr, c->regbase + GPDR_OFFSET);
|
|
}
|
|
}
|
|
#else
|
|
#define pxa_gpio_suspend NULL
|
|
#define pxa_gpio_resume NULL
|
|
#endif
|
|
|
|
struct syscore_ops pxa_gpio_syscore_ops = {
|
|
.suspend = pxa_gpio_suspend,
|
|
.resume = pxa_gpio_resume,
|
|
};
|
|
|
|
static int __init pxa_gpio_sysinit(void)
|
|
{
|
|
register_syscore_ops(&pxa_gpio_syscore_ops);
|
|
return 0;
|
|
}
|
|
postcore_initcall(pxa_gpio_sysinit);
|