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e9de688dac
The MIPS GIC supports 7 local interrupts, 2 of which are the GIC local watchdog and count/compare timer. The remainder are CPU interrupts which may optionally be re-routed through the GIC. GIC hardware IRQs 0-6 are now used for local interrupts while hardware IRQs 7+ are used for external (shared) interrupts. Note that the 5 CPU interrupts may not be re-routable through the GIC. In that case mapping will fail and the vectors reported in C0_IntCtl should be used instead. gic_get_c0_compare_int() and gic_get_c0_perfcount_int() will return the correct IRQ number to use for the C0 timer and perfcounter interrupts based on the routability of those interrupts through the GIC. A separate irq_chip, with callbacks that mask/unmask the local interrupt on all CPUs, is used for the C0 timer and performance counter interrupts since all other platforms do not use the percpu IRQ API for those interrupts. Malta, SEAD-3, and the GIC clockevent driver have been updated to use local interrupts and the R4K clockevent driver has been updated to poll for C0 timer interrupts through the GIC when the GIC is present. Signed-off-by: Andrew Bresticker <abrestic@chromium.org> Acked-by: Jason Cooper <jason@lakedaemon.net> Reviewed-by: Qais Yousef <qais.yousef@imgtec.com> Tested-by: Qais Yousef <qais.yousef@imgtec.com> Cc: Thomas Gleixner <tglx@linutronix.de> Cc: Jeffrey Deans <jeffrey.deans@imgtec.com> Cc: Markos Chandras <markos.chandras@imgtec.com> Cc: Paul Burton <paul.burton@imgtec.com> Cc: Jonas Gorski <jogo@openwrt.org> Cc: John Crispin <blogic@openwrt.org> Cc: David Daney <ddaney.cavm@gmail.com> Cc: linux-mips@linux-mips.org Cc: linux-kernel@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/7819/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
104 lines
2.3 KiB
C
104 lines
2.3 KiB
C
/*
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* This file is subject to the terms and conditions of the GNU General Public
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* License. See the file "COPYING" in the main directory of this archive
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* for more details.
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*
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* Copyright (C) 2013 Imagination Technologies Ltd.
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*/
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#include <linux/clockchips.h>
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#include <linux/interrupt.h>
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#include <linux/percpu.h>
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#include <linux/smp.h>
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#include <linux/irq.h>
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#include <asm/time.h>
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#include <asm/gic.h>
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#include <asm/mips-boards/maltaint.h>
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DEFINE_PER_CPU(struct clock_event_device, gic_clockevent_device);
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int gic_timer_irq_installed;
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static int gic_next_event(unsigned long delta, struct clock_event_device *evt)
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{
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u64 cnt;
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int res;
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cnt = gic_read_count();
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cnt += (u64)delta;
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gic_write_cpu_compare(cnt, cpumask_first(evt->cpumask));
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res = ((int)(gic_read_count() - cnt) >= 0) ? -ETIME : 0;
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return res;
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}
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void gic_set_clock_mode(enum clock_event_mode mode,
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struct clock_event_device *evt)
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{
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/* Nothing to do ... */
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}
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irqreturn_t gic_compare_interrupt(int irq, void *dev_id)
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{
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struct clock_event_device *cd;
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int cpu = smp_processor_id();
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gic_write_compare(gic_read_compare());
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cd = &per_cpu(gic_clockevent_device, cpu);
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cd->event_handler(cd);
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return IRQ_HANDLED;
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}
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struct irqaction gic_compare_irqaction = {
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.handler = gic_compare_interrupt,
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.flags = IRQF_PERCPU | IRQF_TIMER,
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.name = "timer",
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};
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void gic_event_handler(struct clock_event_device *dev)
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{
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}
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int gic_clockevent_init(void)
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{
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unsigned int cpu = smp_processor_id();
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struct clock_event_device *cd;
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unsigned int irq;
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if (!cpu_has_counter || !gic_frequency)
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return -ENXIO;
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irq = MIPS_GIC_IRQ_BASE + GIC_LOCAL_TO_HWIRQ(GIC_LOCAL_INT_COMPARE);
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cd = &per_cpu(gic_clockevent_device, cpu);
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cd->name = "MIPS GIC";
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cd->features = CLOCK_EVT_FEAT_ONESHOT |
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CLOCK_EVT_FEAT_C3STOP;
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clockevent_set_clock(cd, gic_frequency);
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/* Calculate the min / max delta */
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cd->max_delta_ns = clockevent_delta2ns(0x7fffffff, cd);
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cd->min_delta_ns = clockevent_delta2ns(0x300, cd);
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cd->rating = 300;
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cd->irq = irq;
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cd->cpumask = cpumask_of(cpu);
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cd->set_next_event = gic_next_event;
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cd->set_mode = gic_set_clock_mode;
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cd->event_handler = gic_event_handler;
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clockevents_register_device(cd);
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if (!gic_timer_irq_installed) {
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setup_percpu_irq(irq, &gic_compare_irqaction);
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gic_timer_irq_installed = 1;
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}
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enable_percpu_irq(irq, IRQ_TYPE_NONE);
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return 0;
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}
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