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d13ffb5630
Acked-by: Geert Uytterhoeven <geert@linux-m68k.org> Signed-off-by: Al Viro <viro@zeniv.linux.org.uk>
158 lines
4.9 KiB
ArmAsm
158 lines
4.9 KiB
ArmAsm
/* libgcc1 routines for 68000 w/o floating-point hardware.
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Copyright (C) 1994, 1996, 1997, 1998 Free Software Foundation, Inc.
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This file is part of GNU CC.
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GNU CC is free software; you can redistribute it and/or modify it
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under the terms of the GNU General Public License as published by the
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Free Software Foundation; either version 2, or (at your option) any
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later version.
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In addition to the permissions in the GNU General Public License, the
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Free Software Foundation gives you unlimited permission to link the
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compiled version of this file with other programs, and to distribute
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those programs without any restriction coming from the use of this
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file. (The General Public License restrictions do apply in other
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respects; for example, they cover modification of the file, and
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distribution when not linked into another program.)
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This file is distributed in the hope that it will be useful, but
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WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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General Public License for more details. */
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/* As a special exception, if you link this library with files
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compiled with GCC to produce an executable, this does not cause
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the resulting executable to be covered by the GNU General Public License.
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This exception does not however invalidate any other reasons why
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the executable file might be covered by the GNU General Public License. */
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/* Use this one for any 680x0; assumes no floating point hardware.
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The trailing " '" appearing on some lines is for ANSI preprocessors. Yuk.
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Some of this code comes from MINIX, via the folks at ericsson.
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D. V. Henkel-Wallace (gumby@cygnus.com) Fete Bastille, 1992
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*/
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#include <asm/export.h>
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/* These are predefined by new versions of GNU cpp. */
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#ifndef __USER_LABEL_PREFIX__
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#define __USER_LABEL_PREFIX__ _
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#endif
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#ifndef __REGISTER_PREFIX__
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#define __REGISTER_PREFIX__
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#endif
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#ifndef __IMMEDIATE_PREFIX__
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#define __IMMEDIATE_PREFIX__ #
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#endif
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/* ANSI concatenation macros. */
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#define CONCAT1(a, b) CONCAT2(a, b)
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#define CONCAT2(a, b) a ## b
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/* Use the right prefix for global labels. */
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#define SYM(x) CONCAT1 (__USER_LABEL_PREFIX__, x)
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/* Use the right prefix for registers. */
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#define REG(x) CONCAT1 (__REGISTER_PREFIX__, x)
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/* Use the right prefix for immediate values. */
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#define IMM(x) CONCAT1 (__IMMEDIATE_PREFIX__, x)
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#define d0 REG (d0)
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#define d1 REG (d1)
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#define d2 REG (d2)
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#define d3 REG (d3)
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#define d4 REG (d4)
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#define d5 REG (d5)
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#define d6 REG (d6)
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#define d7 REG (d7)
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#define a0 REG (a0)
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#define a1 REG (a1)
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#define a2 REG (a2)
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#define a3 REG (a3)
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#define a4 REG (a4)
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#define a5 REG (a5)
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#define a6 REG (a6)
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#define fp REG (fp)
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#define sp REG (sp)
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.text
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.proc
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.globl SYM (__udivsi3)
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SYM (__udivsi3):
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#if !(defined(__mcf5200__) || defined(__mcoldfire__))
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movel d2, sp@-
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movel sp@(12), d1 /* d1 = divisor */
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movel sp@(8), d0 /* d0 = dividend */
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cmpl IMM (0x10000), d1 /* divisor >= 2 ^ 16 ? */
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jcc L3 /* then try next algorithm */
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movel d0, d2
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clrw d2
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swap d2
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divu d1, d2 /* high quotient in lower word */
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movew d2, d0 /* save high quotient */
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swap d0
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movew sp@(10), d2 /* get low dividend + high rest */
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divu d1, d2 /* low quotient */
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movew d2, d0
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jra L6
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L3: movel d1, d2 /* use d2 as divisor backup */
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L4: lsrl IMM (1), d1 /* shift divisor */
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lsrl IMM (1), d0 /* shift dividend */
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cmpl IMM (0x10000), d1 /* still divisor >= 2 ^ 16 ? */
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jcc L4
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divu d1, d0 /* now we have 16 bit divisor */
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andl IMM (0xffff), d0 /* mask out divisor, ignore remainder */
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/* Multiply the 16 bit tentative quotient with the 32 bit divisor. Because of
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the operand ranges, this might give a 33 bit product. If this product is
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greater than the dividend, the tentative quotient was too large. */
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movel d2, d1
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mulu d0, d1 /* low part, 32 bits */
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swap d2
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mulu d0, d2 /* high part, at most 17 bits */
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swap d2 /* align high part with low part */
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tstw d2 /* high part 17 bits? */
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jne L5 /* if 17 bits, quotient was too large */
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addl d2, d1 /* add parts */
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jcs L5 /* if sum is 33 bits, quotient was too large */
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cmpl sp@(8), d1 /* compare the sum with the dividend */
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jls L6 /* if sum > dividend, quotient was too large */
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L5: subql IMM (1), d0 /* adjust quotient */
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L6: movel sp@+, d2
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rts
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#else /* __mcf5200__ || __mcoldfire__ */
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/* Coldfire implementation of non-restoring division algorithm from
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Hennessy & Patterson, Appendix A. */
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link a6,IMM (-12)
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moveml d2-d4,sp@
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movel a6@(8),d0
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movel a6@(12),d1
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clrl d2 | clear p
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moveq IMM (31),d4
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L1: addl d0,d0 | shift reg pair (p,a) one bit left
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addxl d2,d2
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movl d2,d3 | subtract b from p, store in tmp.
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subl d1,d3
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jcs L2 | if no carry,
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bset IMM (0),d0 | set the low order bit of a to 1,
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movl d3,d2 | and store tmp in p.
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L2: subql IMM (1),d4
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jcc L1
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moveml sp@,d2-d4 | restore data registers
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unlk a6 | and return
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rts
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#endif /* __mcf5200__ || __mcoldfire__ */
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EXPORT_SYMBOL(__udivsi3)
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