mirror of
https://github.com/edk2-porting/linux-next.git
synced 2024-12-27 14:43:58 +08:00
1394f03221
This adds support for the Analog Devices Blackfin processor architecture, and currently supports the BF533, BF532, BF531, BF537, BF536, BF534, and BF561 (Dual Core) devices, with a variety of development platforms including those avaliable from Analog Devices (BF533-EZKit, BF533-STAMP, BF537-STAMP, BF561-EZKIT), and Bluetechnix! Tinyboards. The Blackfin architecture was jointly developed by Intel and Analog Devices Inc. (ADI) as the Micro Signal Architecture (MSA) core and introduced it in December of 2000. Since then ADI has put this core into its Blackfin processor family of devices. The Blackfin core has the advantages of a clean, orthogonal,RISC-like microprocessor instruction set. It combines a dual-MAC (Multiply/Accumulate), state-of-the-art signal processing engine and single-instruction, multiple-data (SIMD) multimedia capabilities into a single instruction-set architecture. The Blackfin architecture, including the instruction set, is described by the ADSP-BF53x/BF56x Blackfin Processor Programming Reference http://blackfin.uclinux.org/gf/download/frsrelease/29/2549/Blackfin_PRM.pdf The Blackfin processor is already supported by major releases of gcc, and there are binary and source rpms/tarballs for many architectures at: http://blackfin.uclinux.org/gf/project/toolchain/frs There is complete documentation, including "getting started" guides available at: http://docs.blackfin.uclinux.org/ which provides links to the sources and patches you will need in order to set up a cross-compiling environment for bfin-linux-uclibc This patch, as well as the other patches (toolchain, distribution, uClibc) are actively supported by Analog Devices Inc, at: http://blackfin.uclinux.org/ We have tested this on LTP, and our test plan (including pass/fails) can be found at: http://docs.blackfin.uclinux.org/doku.php?id=testing_the_linux_kernel [m.kozlowski@tuxland.pl: balance parenthesis in blackfin header files] Signed-off-by: Bryan Wu <bryan.wu@analog.com> Signed-off-by: Mariusz Kozlowski <m.kozlowski@tuxland.pl> Signed-off-by: Aubrey Li <aubrey.li@analog.com> Signed-off-by: Jie Zhang <jie.zhang@analog.com> Signed-off-by: Andrew Morton <akpm@linux-foundation.org> Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
145 lines
3.0 KiB
C
145 lines
3.0 KiB
C
#ifndef __ARCH_BLACKFIN_ATOMIC__
|
|
#define __ARCH_BLACKFIN_ATOMIC__
|
|
|
|
#include <asm/system.h> /* local_irq_XXX() */
|
|
|
|
/*
|
|
* Atomic operations that C can't guarantee us. Useful for
|
|
* resource counting etc..
|
|
*
|
|
* Generally we do not concern about SMP BFIN systems, so we don't have
|
|
* to deal with that.
|
|
*
|
|
* Tony Kou (tonyko@lineo.ca) Lineo Inc. 2001
|
|
*/
|
|
|
|
typedef struct {
|
|
int counter;
|
|
} atomic_t;
|
|
#define ATOMIC_INIT(i) { (i) }
|
|
|
|
#define atomic_read(v) ((v)->counter)
|
|
#define atomic_set(v, i) (((v)->counter) = i)
|
|
|
|
static __inline__ void atomic_add(int i, atomic_t * v)
|
|
{
|
|
long flags;
|
|
|
|
local_irq_save(flags);
|
|
v->counter += i;
|
|
local_irq_restore(flags);
|
|
}
|
|
|
|
static __inline__ void atomic_sub(int i, atomic_t * v)
|
|
{
|
|
long flags;
|
|
|
|
local_irq_save(flags);
|
|
v->counter -= i;
|
|
local_irq_restore(flags);
|
|
|
|
}
|
|
|
|
static inline int atomic_add_return(int i, atomic_t * v)
|
|
{
|
|
int __temp = 0;
|
|
long flags;
|
|
|
|
local_irq_save(flags);
|
|
v->counter += i;
|
|
__temp = v->counter;
|
|
local_irq_restore(flags);
|
|
|
|
|
|
return __temp;
|
|
}
|
|
|
|
#define atomic_add_negative(a, v) (atomic_add_return((a), (v)) < 0)
|
|
static inline int atomic_sub_return(int i, atomic_t * v)
|
|
{
|
|
int __temp = 0;
|
|
long flags;
|
|
|
|
local_irq_save(flags);
|
|
v->counter -= i;
|
|
__temp = v->counter;
|
|
local_irq_restore(flags);
|
|
|
|
return __temp;
|
|
}
|
|
|
|
static __inline__ void atomic_inc(volatile atomic_t * v)
|
|
{
|
|
long flags;
|
|
|
|
local_irq_save(flags);
|
|
v->counter++;
|
|
local_irq_restore(flags);
|
|
}
|
|
|
|
#define atomic_cmpxchg(v, o, n) ((int)cmpxchg(&((v)->counter), (o), (n)))
|
|
#define atomic_xchg(v, new) (xchg(&((v)->counter), new))
|
|
|
|
#define atomic_add_unless(v, a, u) \
|
|
({ \
|
|
int c, old; \
|
|
c = atomic_read(v); \
|
|
while (c != (u) && (old = atomic_cmpxchg((v), c, c + (a))) != c) \
|
|
c = old; \
|
|
c != (u); \
|
|
})
|
|
#define atomic_inc_not_zero(v) atomic_add_unless((v), 1, 0)
|
|
|
|
static __inline__ void atomic_dec(volatile atomic_t * v)
|
|
{
|
|
long flags;
|
|
|
|
local_irq_save(flags);
|
|
v->counter--;
|
|
local_irq_restore(flags);
|
|
}
|
|
|
|
static __inline__ void atomic_clear_mask(unsigned int mask, atomic_t * v)
|
|
{
|
|
long flags;
|
|
|
|
local_irq_save(flags);
|
|
v->counter &= ~mask;
|
|
local_irq_restore(flags);
|
|
}
|
|
|
|
static __inline__ void atomic_set_mask(unsigned int mask, atomic_t * v)
|
|
{
|
|
long flags;
|
|
|
|
local_irq_save(flags);
|
|
v->counter |= mask;
|
|
local_irq_restore(flags);
|
|
}
|
|
|
|
/* Atomic operations are already serializing */
|
|
#define smp_mb__before_atomic_dec() barrier()
|
|
#define smp_mb__after_atomic_dec() barrier()
|
|
#define smp_mb__before_atomic_inc() barrier()
|
|
#define smp_mb__after_atomic_inc() barrier()
|
|
|
|
#define atomic_dec_return(v) atomic_sub_return(1,(v))
|
|
#define atomic_inc_return(v) atomic_add_return(1,(v))
|
|
|
|
/*
|
|
* atomic_inc_and_test - increment and test
|
|
* @v: pointer of type atomic_t
|
|
*
|
|
* Atomically increments @v by 1
|
|
* and returns true if the result is zero, or false for all
|
|
* other cases.
|
|
*/
|
|
#define atomic_inc_and_test(v) (atomic_inc_return(v) == 0)
|
|
|
|
#define atomic_sub_and_test(i,v) (atomic_sub_return((i), (v)) == 0)
|
|
#define atomic_dec_and_test(v) (atomic_sub_return(1, (v)) == 0)
|
|
|
|
#include <asm-generic/atomic.h>
|
|
|
|
#endif /* __ARCH_BLACKFIN_ATOMIC __ */
|