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eeb3d68b6c
Add DDR EDAC driver for ARM-based compatible controllers. Both big-endian and little-endian are supported, as specified in device tree. Signed-off-by: York Sun <york.sun@nxp.com> Cc: linux-arm-kernel@lists.infradead.org Cc: linux-edac <linux-edac@vger.kernel.org> Link: http://lkml.kernel.org/r/1471990465-27443-1-git-send-email-york.sun@nxp.com Signed-off-by: Borislav Petkov <bp@suse.de>
74 lines
1.6 KiB
C
74 lines
1.6 KiB
C
/*
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* Freescale Memory Controller kernel module
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*
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* Author: York Sun <york.sun@nxp.com>
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*
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* Copyright 2016 NXP Semiconductor
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*
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* Derived from mpc85xx_edac.c
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* Author: Dave Jiang <djiang@mvista.com>
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*
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* 2006-2007 (c) MontaVista Software, Inc. This file is licensed under
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* the terms of the GNU General Public License version 2. This program
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* is licensed "as is" without any warranty of any kind, whether express
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* or implied.
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*/
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#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
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#include "edac_core.h"
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#include "fsl_ddr_edac.h"
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static const struct of_device_id fsl_ddr_mc_err_of_match[] = {
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{ .compatible = "fsl,qoriq-memory-controller", },
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{},
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};
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MODULE_DEVICE_TABLE(of, fsl_ddr_mc_err_of_match);
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static struct platform_driver fsl_ddr_mc_err_driver = {
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.probe = fsl_mc_err_probe,
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.remove = fsl_mc_err_remove,
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.driver = {
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.name = "fsl_ddr_mc_err",
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.of_match_table = fsl_ddr_mc_err_of_match,
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},
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};
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static int __init fsl_ddr_mc_init(void)
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{
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int res;
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/* make sure error reporting method is sane */
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switch (edac_op_state) {
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case EDAC_OPSTATE_POLL:
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case EDAC_OPSTATE_INT:
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break;
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default:
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edac_op_state = EDAC_OPSTATE_INT;
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break;
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}
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res = platform_driver_register(&fsl_ddr_mc_err_driver);
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if (res) {
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pr_err("MC fails to register\n");
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return res;
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}
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return 0;
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}
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module_init(fsl_ddr_mc_init);
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static void __exit fsl_ddr_mc_exit(void)
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{
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platform_driver_unregister(&fsl_ddr_mc_err_driver);
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}
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module_exit(fsl_ddr_mc_exit);
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MODULE_LICENSE("GPL");
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MODULE_AUTHOR("NXP Semiconductor");
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module_param(edac_op_state, int, 0444);
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MODULE_PARM_DESC(edac_op_state,
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"EDAC Error Reporting state: 0=Poll, 2=Interrupt");
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