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61890ccaef
This patch adds driver for MediaTek's Media Data Path ver.3 (MDP3).
It provides the following functions:
color transform, format conversion, resize, crop, rotate, flip
and additional image quality enhancement.
The MDP3 driver is mainly used for Google Chromebook products to
import the new architecture to set the HW settings as shown below:
User -> V4L2 framework
-> MDP3 driver -> SCP (setting calculations)
-> MDP3 driver -> CMDQ (GCE driver) -> HW
Each modules' related operation control is sited in mtk-mdp3-comp.c
Each modules' register table is defined in file with "mdp_reg_" prefix
GCE related API, operation control sited in mtk-mdp3-cmdq.c
V4L2 m2m device functions are implemented in mtk-mdp3-m2m.c
Probe, power, suspend/resume, system level functions are defined in
mtk-mdp3-core.c
[hverkuil: add 'depends on REMOTEPROC']
Signed-off-by: Ping-Hsun Wu <ping-hsun.wu@mediatek.com>
Signed-off-by: daoyuan huang <daoyuan.huang@mediatek.com>
Signed-off-by: Moudy Ho <moudy.ho@mediatek.com>
Tested-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Signed-off-by: Hans Verkuil <hverkuil-cisco@xs4all.nl>
Signed-off-by: Mauro Carvalho Chehab <mchehab@kernel.org>
48 lines
1.6 KiB
C
48 lines
1.6 KiB
C
/* SPDX-License-Identifier: GPL-2.0-only */
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/*
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* Copyright (c) 2022 MediaTek Inc.
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* Author: Ping-Hsun Wu <ping-hsun.wu@mediatek.com>
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*/
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#ifndef __MDP_REG_WDMA_H__
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#define __MDP_REG_WDMA_H__
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#define WDMA_EN 0x008
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#define WDMA_RST 0x00c
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#define WDMA_CFG 0x014
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#define WDMA_SRC_SIZE 0x018
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#define WDMA_CLIP_SIZE 0x01c
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#define WDMA_CLIP_COORD 0x020
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#define WDMA_DST_W_IN_BYTE 0x028
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#define WDMA_ALPHA 0x02c
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#define WDMA_BUF_CON2 0x03c
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#define WDMA_DST_UV_PITCH 0x078
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#define WDMA_DST_ADDR_OFFSET 0x080
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#define WDMA_DST_U_ADDR_OFFSET 0x084
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#define WDMA_DST_V_ADDR_OFFSET 0x088
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#define WDMA_FLOW_CTRL_DBG 0x0a0
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#define WDMA_DST_ADDR 0xf00
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#define WDMA_DST_U_ADDR 0xf04
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#define WDMA_DST_V_ADDR 0xf08
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/* MASK */
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#define WDMA_EN_MASK 0x00000001
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#define WDMA_RST_MASK 0x00000001
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#define WDMA_CFG_MASK 0xff03bff0
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#define WDMA_SRC_SIZE_MASK 0x3fff3fff
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#define WDMA_CLIP_SIZE_MASK 0x3fff3fff
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#define WDMA_CLIP_COORD_MASK 0x3fff3fff
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#define WDMA_DST_W_IN_BYTE_MASK 0x0000ffff
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#define WDMA_ALPHA_MASK 0x800000ff
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#define WDMA_BUF_CON2_MASK 0xffffffff
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#define WDMA_DST_UV_PITCH_MASK 0x0000ffff
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#define WDMA_DST_ADDR_OFFSET_MASK 0x0fffffff
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#define WDMA_DST_U_ADDR_OFFSET_MASK 0x0fffffff
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#define WDMA_DST_V_ADDR_OFFSET_MASK 0x0fffffff
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#define WDMA_FLOW_CTRL_DBG_MASK 0x0000f3ff
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#define WDMA_DST_ADDR_MASK 0xffffffff
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#define WDMA_DST_U_ADDR_MASK 0xffffffff
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#define WDMA_DST_V_ADDR_MASK 0xffffffff
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#endif // __MDP_REG_WDMA_H__
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