This patch is a take two of adding full functionality to PLL1 on
AT32AP7000. This allows board-specific code and drivers to configure
and enable PLL1. This is useful when precise control over the
frequency of e.g. a genclock is needed and requested by users for the
ABDAC device.
The patch is based upon previous patches from both Haavard Skinnemoen
and David Brownell.
Signed-off-by: Hans-Christian Egtvedt <hcegtvedt@atmel.com>
Signed-off-by: Haavard Skinnemoen <hskinnemoen@atmel.com>
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