mirror of
https://github.com/edk2-porting/linux-next.git
synced 2024-12-27 06:34:11 +08:00
eab4002660
This tag contains the patches I'd like to target for 5.7. It has a handful of
new features:
* Partial support for the Kendryte K210. There are still a few outstanding
issues that I have patches for, but I don't actually have a board to test
them so they're not included yet.
* SBI v0.2 support.
* Fixes to support for building with LLVM-based toolchains. The resulting
images are known not to boot yet.
This builds and boots for me. There is one merge conflict, it's just a Kconfig
merge issue. I can publish a resolved branch if you'd like.
I don't anticipate a part two, but I'll probably have something early in the
RCs to finish up the K210 support.
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Merge tag 'riscv-for-linus-5.7' of git://git.kernel.org/pub/scm/linux/kernel/git/riscv/linux
Pull RISC-V updates from Palmer Dabbelt:
"This contains a handful of new features:
- Partial support for the Kendryte K210.
There are still a few outstanding issues that I have patches for,
but I don't actually have a board to test them so they're not
included yet.
- SBI v0.2 support.
- Fixes to support for building with LLVM-based toolchains. The
resulting images are known not to boot yet.
I don't anticipate a part two, but I'll probably have something early
in the RCs to finish up the K210 support"
* tag 'riscv-for-linus-5.7' of git://git.kernel.org/pub/scm/linux/kernel/git/riscv/linux: (38 commits)
riscv: create a loader.bin boot image for Kendryte SoC
riscv: Kendryte K210 default config
riscv: Add Kendryte K210 device tree
riscv: Select required drivers for Kendryte SOC
riscv: Add Kendryte K210 SoC support
riscv: Add SOC early init support
riscv: Unaligned load/store handling for M_MODE
RISC-V: Support cpu hotplug
RISC-V: Add supported for ordered booting method using HSM
RISC-V: Add SBI HSM extension definitions
RISC-V: Export SBI error to linux error mapping function
RISC-V: Add cpu_ops and modify default booting method
RISC-V: Move relocate and few other functions out of __init
RISC-V: Implement new SBI v0.2 extensions
RISC-V: Introduce a new config for SBI v0.1
RISC-V: Add SBI v0.2 extension definitions
RISC-V: Add basic support for SBI v0.2
RISC-V: Mark existing SBI as 0.1 SBI.
riscv: Use macro definition instead of magic number
riscv: Add support to dump the kernel page tables
...
431 lines
11 KiB
ArmAsm
431 lines
11 KiB
ArmAsm
/* SPDX-License-Identifier: GPL-2.0-only */
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/*
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* Copyright (C) 2012 Regents of the University of California
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* Copyright (C) 2017 SiFive
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*/
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#include <linux/init.h>
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#include <linux/linkage.h>
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#include <asm/asm.h>
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#include <asm/csr.h>
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#include <asm/unistd.h>
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#include <asm/thread_info.h>
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#include <asm/asm-offsets.h>
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#if !IS_ENABLED(CONFIG_PREEMPTION)
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.set resume_kernel, restore_all
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#endif
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ENTRY(handle_exception)
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/*
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* If coming from userspace, preserve the user thread pointer and load
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* the kernel thread pointer. If we came from the kernel, the scratch
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* register will contain 0, and we should continue on the current TP.
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*/
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csrrw tp, CSR_SCRATCH, tp
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bnez tp, _save_context
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_restore_kernel_tpsp:
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csrr tp, CSR_SCRATCH
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REG_S sp, TASK_TI_KERNEL_SP(tp)
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_save_context:
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REG_S sp, TASK_TI_USER_SP(tp)
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REG_L sp, TASK_TI_KERNEL_SP(tp)
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addi sp, sp, -(PT_SIZE_ON_STACK)
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REG_S x1, PT_RA(sp)
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REG_S x3, PT_GP(sp)
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REG_S x5, PT_T0(sp)
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REG_S x6, PT_T1(sp)
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REG_S x7, PT_T2(sp)
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REG_S x8, PT_S0(sp)
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REG_S x9, PT_S1(sp)
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REG_S x10, PT_A0(sp)
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REG_S x11, PT_A1(sp)
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REG_S x12, PT_A2(sp)
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REG_S x13, PT_A3(sp)
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REG_S x14, PT_A4(sp)
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REG_S x15, PT_A5(sp)
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REG_S x16, PT_A6(sp)
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REG_S x17, PT_A7(sp)
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REG_S x18, PT_S2(sp)
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REG_S x19, PT_S3(sp)
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REG_S x20, PT_S4(sp)
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REG_S x21, PT_S5(sp)
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REG_S x22, PT_S6(sp)
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REG_S x23, PT_S7(sp)
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REG_S x24, PT_S8(sp)
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REG_S x25, PT_S9(sp)
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REG_S x26, PT_S10(sp)
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REG_S x27, PT_S11(sp)
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REG_S x28, PT_T3(sp)
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REG_S x29, PT_T4(sp)
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REG_S x30, PT_T5(sp)
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REG_S x31, PT_T6(sp)
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/*
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* Disable user-mode memory access as it should only be set in the
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* actual user copy routines.
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*
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* Disable the FPU to detect illegal usage of floating point in kernel
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* space.
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*/
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li t0, SR_SUM | SR_FS
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REG_L s0, TASK_TI_USER_SP(tp)
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csrrc s1, CSR_STATUS, t0
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csrr s2, CSR_EPC
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csrr s3, CSR_TVAL
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csrr s4, CSR_CAUSE
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csrr s5, CSR_SCRATCH
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REG_S s0, PT_SP(sp)
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REG_S s1, PT_STATUS(sp)
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REG_S s2, PT_EPC(sp)
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REG_S s3, PT_BADADDR(sp)
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REG_S s4, PT_CAUSE(sp)
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REG_S s5, PT_TP(sp)
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/*
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* Set the scratch register to 0, so that if a recursive exception
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* occurs, the exception vector knows it came from the kernel
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*/
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csrw CSR_SCRATCH, x0
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/* Load the global pointer */
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.option push
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.option norelax
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la gp, __global_pointer$
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.option pop
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la ra, ret_from_exception
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/*
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* MSB of cause differentiates between
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* interrupts and exceptions
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*/
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bge s4, zero, 1f
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/* Handle interrupts */
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move a0, sp /* pt_regs */
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tail do_IRQ
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1:
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/*
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* Exceptions run with interrupts enabled or disabled depending on the
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* state of SR_PIE in m/sstatus.
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*/
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andi t0, s1, SR_PIE
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beqz t0, 1f
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csrs CSR_STATUS, SR_IE
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1:
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/* Handle syscalls */
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li t0, EXC_SYSCALL
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beq s4, t0, handle_syscall
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/* Handle other exceptions */
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slli t0, s4, RISCV_LGPTR
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la t1, excp_vect_table
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la t2, excp_vect_table_end
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move a0, sp /* pt_regs */
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add t0, t1, t0
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/* Check if exception code lies within bounds */
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bgeu t0, t2, 1f
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REG_L t0, 0(t0)
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jr t0
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1:
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tail do_trap_unknown
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handle_syscall:
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/* save the initial A0 value (needed in signal handlers) */
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REG_S a0, PT_ORIG_A0(sp)
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/*
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* Advance SEPC to avoid executing the original
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* scall instruction on sret
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*/
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addi s2, s2, 0x4
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REG_S s2, PT_EPC(sp)
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/* Trace syscalls, but only if requested by the user. */
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REG_L t0, TASK_TI_FLAGS(tp)
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andi t0, t0, _TIF_SYSCALL_WORK
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bnez t0, handle_syscall_trace_enter
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check_syscall_nr:
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/* Check to make sure we don't jump to a bogus syscall number. */
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li t0, __NR_syscalls
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la s0, sys_ni_syscall
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/*
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* Syscall number held in a7.
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* If syscall number is above allowed value, redirect to ni_syscall.
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*/
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bge a7, t0, 1f
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/*
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* Check if syscall is rejected by tracer, i.e., a7 == -1.
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* If yes, we pretend it was executed.
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*/
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li t1, -1
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beq a7, t1, ret_from_syscall_rejected
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blt a7, t1, 1f
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/* Call syscall */
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la s0, sys_call_table
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slli t0, a7, RISCV_LGPTR
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add s0, s0, t0
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REG_L s0, 0(s0)
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1:
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jalr s0
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ret_from_syscall:
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/* Set user a0 to kernel a0 */
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REG_S a0, PT_A0(sp)
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/*
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* We didn't execute the actual syscall.
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* Seccomp already set return value for the current task pt_regs.
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* (If it was configured with SECCOMP_RET_ERRNO/TRACE)
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*/
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ret_from_syscall_rejected:
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/* Trace syscalls, but only if requested by the user. */
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REG_L t0, TASK_TI_FLAGS(tp)
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andi t0, t0, _TIF_SYSCALL_WORK
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bnez t0, handle_syscall_trace_exit
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ret_from_exception:
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REG_L s0, PT_STATUS(sp)
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csrc CSR_STATUS, SR_IE
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#ifdef CONFIG_RISCV_M_MODE
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/* the MPP value is too large to be used as an immediate arg for addi */
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li t0, SR_MPP
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and s0, s0, t0
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#else
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andi s0, s0, SR_SPP
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#endif
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bnez s0, resume_kernel
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resume_userspace:
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/* Interrupts must be disabled here so flags are checked atomically */
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REG_L s0, TASK_TI_FLAGS(tp) /* current_thread_info->flags */
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andi s1, s0, _TIF_WORK_MASK
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bnez s1, work_pending
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/* Save unwound kernel stack pointer in thread_info */
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addi s0, sp, PT_SIZE_ON_STACK
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REG_S s0, TASK_TI_KERNEL_SP(tp)
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/*
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* Save TP into the scratch register , so we can find the kernel data
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* structures again.
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*/
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csrw CSR_SCRATCH, tp
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restore_all:
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REG_L a0, PT_STATUS(sp)
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/*
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* The current load reservation is effectively part of the processor's
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* state, in the sense that load reservations cannot be shared between
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* different hart contexts. We can't actually save and restore a load
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* reservation, so instead here we clear any existing reservation --
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* it's always legal for implementations to clear load reservations at
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* any point (as long as the forward progress guarantee is kept, but
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* we'll ignore that here).
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*
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* Dangling load reservations can be the result of taking a trap in the
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* middle of an LR/SC sequence, but can also be the result of a taken
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* forward branch around an SC -- which is how we implement CAS. As a
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* result we need to clear reservations between the last CAS and the
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* jump back to the new context. While it is unlikely the store
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* completes, implementations are allowed to expand reservations to be
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* arbitrarily large.
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*/
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REG_L a2, PT_EPC(sp)
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REG_SC x0, a2, PT_EPC(sp)
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csrw CSR_STATUS, a0
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csrw CSR_EPC, a2
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REG_L x1, PT_RA(sp)
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REG_L x3, PT_GP(sp)
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REG_L x4, PT_TP(sp)
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REG_L x5, PT_T0(sp)
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REG_L x6, PT_T1(sp)
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REG_L x7, PT_T2(sp)
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REG_L x8, PT_S0(sp)
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REG_L x9, PT_S1(sp)
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REG_L x10, PT_A0(sp)
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REG_L x11, PT_A1(sp)
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REG_L x12, PT_A2(sp)
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REG_L x13, PT_A3(sp)
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REG_L x14, PT_A4(sp)
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REG_L x15, PT_A5(sp)
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REG_L x16, PT_A6(sp)
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REG_L x17, PT_A7(sp)
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REG_L x18, PT_S2(sp)
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REG_L x19, PT_S3(sp)
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REG_L x20, PT_S4(sp)
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REG_L x21, PT_S5(sp)
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REG_L x22, PT_S6(sp)
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REG_L x23, PT_S7(sp)
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REG_L x24, PT_S8(sp)
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REG_L x25, PT_S9(sp)
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REG_L x26, PT_S10(sp)
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REG_L x27, PT_S11(sp)
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REG_L x28, PT_T3(sp)
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REG_L x29, PT_T4(sp)
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REG_L x30, PT_T5(sp)
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REG_L x31, PT_T6(sp)
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REG_L x2, PT_SP(sp)
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#ifdef CONFIG_RISCV_M_MODE
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mret
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#else
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sret
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#endif
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#if IS_ENABLED(CONFIG_PREEMPTION)
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resume_kernel:
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REG_L s0, TASK_TI_PREEMPT_COUNT(tp)
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bnez s0, restore_all
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REG_L s0, TASK_TI_FLAGS(tp)
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andi s0, s0, _TIF_NEED_RESCHED
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beqz s0, restore_all
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call preempt_schedule_irq
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j restore_all
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#endif
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work_pending:
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/* Enter slow path for supplementary processing */
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la ra, ret_from_exception
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andi s1, s0, _TIF_NEED_RESCHED
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bnez s1, work_resched
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work_notifysig:
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/* Handle pending signals and notify-resume requests */
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csrs CSR_STATUS, SR_IE /* Enable interrupts for do_notify_resume() */
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move a0, sp /* pt_regs */
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move a1, s0 /* current_thread_info->flags */
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tail do_notify_resume
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work_resched:
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tail schedule
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/* Slow paths for ptrace. */
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handle_syscall_trace_enter:
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move a0, sp
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call do_syscall_trace_enter
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move t0, a0
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REG_L a0, PT_A0(sp)
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REG_L a1, PT_A1(sp)
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REG_L a2, PT_A2(sp)
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REG_L a3, PT_A3(sp)
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REG_L a4, PT_A4(sp)
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REG_L a5, PT_A5(sp)
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REG_L a6, PT_A6(sp)
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REG_L a7, PT_A7(sp)
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bnez t0, ret_from_syscall_rejected
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j check_syscall_nr
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handle_syscall_trace_exit:
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move a0, sp
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call do_syscall_trace_exit
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j ret_from_exception
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END(handle_exception)
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ENTRY(ret_from_fork)
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la ra, ret_from_exception
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tail schedule_tail
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ENDPROC(ret_from_fork)
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ENTRY(ret_from_kernel_thread)
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call schedule_tail
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/* Call fn(arg) */
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la ra, ret_from_exception
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move a0, s1
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jr s0
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ENDPROC(ret_from_kernel_thread)
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/*
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* Integer register context switch
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* The callee-saved registers must be saved and restored.
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*
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* a0: previous task_struct (must be preserved across the switch)
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* a1: next task_struct
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*
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* The value of a0 and a1 must be preserved by this function, as that's how
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* arguments are passed to schedule_tail.
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*/
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ENTRY(__switch_to)
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/* Save context into prev->thread */
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li a4, TASK_THREAD_RA
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add a3, a0, a4
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add a4, a1, a4
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REG_S ra, TASK_THREAD_RA_RA(a3)
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REG_S sp, TASK_THREAD_SP_RA(a3)
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REG_S s0, TASK_THREAD_S0_RA(a3)
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REG_S s1, TASK_THREAD_S1_RA(a3)
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REG_S s2, TASK_THREAD_S2_RA(a3)
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REG_S s3, TASK_THREAD_S3_RA(a3)
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REG_S s4, TASK_THREAD_S4_RA(a3)
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REG_S s5, TASK_THREAD_S5_RA(a3)
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REG_S s6, TASK_THREAD_S6_RA(a3)
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REG_S s7, TASK_THREAD_S7_RA(a3)
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REG_S s8, TASK_THREAD_S8_RA(a3)
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REG_S s9, TASK_THREAD_S9_RA(a3)
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REG_S s10, TASK_THREAD_S10_RA(a3)
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REG_S s11, TASK_THREAD_S11_RA(a3)
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/* Restore context from next->thread */
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REG_L ra, TASK_THREAD_RA_RA(a4)
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REG_L sp, TASK_THREAD_SP_RA(a4)
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REG_L s0, TASK_THREAD_S0_RA(a4)
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REG_L s1, TASK_THREAD_S1_RA(a4)
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REG_L s2, TASK_THREAD_S2_RA(a4)
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REG_L s3, TASK_THREAD_S3_RA(a4)
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REG_L s4, TASK_THREAD_S4_RA(a4)
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REG_L s5, TASK_THREAD_S5_RA(a4)
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REG_L s6, TASK_THREAD_S6_RA(a4)
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REG_L s7, TASK_THREAD_S7_RA(a4)
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REG_L s8, TASK_THREAD_S8_RA(a4)
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REG_L s9, TASK_THREAD_S9_RA(a4)
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REG_L s10, TASK_THREAD_S10_RA(a4)
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REG_L s11, TASK_THREAD_S11_RA(a4)
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/* Swap the CPU entry around. */
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lw a3, TASK_TI_CPU(a0)
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lw a4, TASK_TI_CPU(a1)
|
|
sw a3, TASK_TI_CPU(a1)
|
|
sw a4, TASK_TI_CPU(a0)
|
|
#if TASK_TI != 0
|
|
#error "TASK_TI != 0: tp will contain a 'struct thread_info', not a 'struct task_struct' so get_current() won't work."
|
|
addi tp, a1, TASK_TI
|
|
#else
|
|
move tp, a1
|
|
#endif
|
|
ret
|
|
ENDPROC(__switch_to)
|
|
|
|
#ifndef CONFIG_MMU
|
|
#define do_page_fault do_trap_unknown
|
|
#endif
|
|
|
|
.section ".rodata"
|
|
/* Exception vector table */
|
|
ENTRY(excp_vect_table)
|
|
RISCV_PTR do_trap_insn_misaligned
|
|
RISCV_PTR do_trap_insn_fault
|
|
RISCV_PTR do_trap_insn_illegal
|
|
RISCV_PTR do_trap_break
|
|
RISCV_PTR do_trap_load_misaligned
|
|
RISCV_PTR do_trap_load_fault
|
|
RISCV_PTR do_trap_store_misaligned
|
|
RISCV_PTR do_trap_store_fault
|
|
RISCV_PTR do_trap_ecall_u /* system call, gets intercepted */
|
|
RISCV_PTR do_trap_ecall_s
|
|
RISCV_PTR do_trap_unknown
|
|
RISCV_PTR do_trap_ecall_m
|
|
RISCV_PTR do_page_fault /* instruction page fault */
|
|
RISCV_PTR do_page_fault /* load page fault */
|
|
RISCV_PTR do_trap_unknown
|
|
RISCV_PTR do_page_fault /* store page fault */
|
|
excp_vect_table_end:
|
|
END(excp_vect_table)
|
|
|
|
#ifndef CONFIG_MMU
|
|
ENTRY(__user_rt_sigreturn)
|
|
li a7, __NR_rt_sigreturn
|
|
scall
|
|
END(__user_rt_sigreturn)
|
|
#endif
|