Andrew Bresticker 35399dda01 clk: exynos5250: add clock ID for div_pcm0 ... There is no gate for the PCM clock input to the AudioSS block, so the parent of sclk_pcm is div_pcm0. Add a clock ID for it so that we can reference it in device trees. Signed-off-by: Andrew Bresticker <abrestic@chromium.org> Reviewed-by: Tomasz Figa <t.figa@samsung.com> Acked-by: Mike Turquette <mturquette@linaro.org> Acked-by: Kukjin Kim <kgene.kim@samsung.com> Signed-off-by: Tomasz Figa <t.figa@samsung.com>		2014-01-08 18:02:42 +01:00
..
clk-exynos4.c	clk: exynos4: replace clock ID private enums with IDs from DT header	2014-01-08 18:02:38 +01:00
clk-exynos5250.c	clk: exynos5250: add clock ID for div_pcm0	2014-01-08 18:02:42 +01:00
clk-exynos5420.c	clk: exynos5420: replace clock ID private enums with IDs from DT header	2014-01-08 18:02:39 +01:00
clk-exynos5440.c	clk: exynos5440: replace clock ID private enums with IDs from DT header	2014-01-08 18:02:40 +01:00
clk-exynos-audss.c	clk: exynos-audss: allow input clocks to be specified in device tree	2014-01-08 18:02:41 +01:00
clk-pll.c	clk: samsung: pll: Add support for rate configuration of PLL46xx	2013-09-06 13:33:47 -07:00
clk-pll.h	clk: samsung: pll: Add support for rate configuration of PLL46xx	2013-09-06 13:33:47 -07:00
clk-s3c64xx.c	clk: s3c64xx: Fix incorrect placement of __initdata	2013-08-27 18:36:20 -07:00
clk.c	clk: samsung: Modify _get_rate() helper to use __clk_lookup()	2013-09-06 13:33:15 -07:00
clk.h	clk: add CLK_SET_RATE_NO_REPARENT flag	2013-08-19 12:27:17 -07:00
Makefile	ARM: S3C64XX: Migrate clock handling to Common Clock Framework	2013-09-17 06:47:36 +09:00