mirror of
https://github.com/edk2-porting/linux-next.git
synced 2024-12-25 05:34:00 +08:00
bba2e87126
It fixes the following Smatch static check warning:
drivers/pinctrl/zte/pinctrl-zx.c:338 zx_pinctrl_build_state()
warn: passing devm_ allocated variable to kfree.
As we will be calling krealloc() on pointer 'functions', which means
kfree() will be called in there, devm_kzalloc() shouldn't be used with
the allocation in the first place. Fix the warning by calling kcalloc()
and managing the free procedure in error path on our own.
Reported-by: Dan Carpenter <dan.carpenter@oracle.com>
Fixes: cbff0c4d27
("pinctrl: add ZTE ZX pinctrl driver support")
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
450 lines
11 KiB
C
450 lines
11 KiB
C
/*
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* Copyright (C) 2017 Sanechips Technology Co., Ltd.
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* Copyright 2017 Linaro Ltd.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#include <linux/io.h>
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#include <linux/of.h>
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#include <linux/of_address.h>
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#include <linux/of_device.h>
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#include <linux/pinctrl/pinctrl.h>
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#include <linux/pinctrl/pinconf-generic.h>
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#include <linux/pinctrl/pinmux.h>
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#include <linux/platform_device.h>
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#include <linux/slab.h>
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#include "../core.h"
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#include "../pinctrl-utils.h"
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#include "../pinmux.h"
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#include "pinctrl-zx.h"
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#define ZX_PULL_DOWN BIT(0)
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#define ZX_PULL_UP BIT(1)
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#define ZX_INPUT_ENABLE BIT(3)
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#define ZX_DS_SHIFT 4
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#define ZX_DS_MASK (0x7 << ZX_DS_SHIFT)
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#define ZX_DS_VALUE(x) (((x) << ZX_DS_SHIFT) & ZX_DS_MASK)
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#define ZX_SLEW BIT(8)
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struct zx_pinctrl {
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struct pinctrl_dev *pctldev;
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struct device *dev;
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void __iomem *base;
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void __iomem *aux_base;
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spinlock_t lock;
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struct zx_pinctrl_soc_info *info;
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};
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static int zx_dt_node_to_map(struct pinctrl_dev *pctldev,
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struct device_node *np_config,
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struct pinctrl_map **map, u32 *num_maps)
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{
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return pinconf_generic_dt_node_to_map(pctldev, np_config, map,
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num_maps, PIN_MAP_TYPE_INVALID);
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}
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static const struct pinctrl_ops zx_pinctrl_ops = {
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.dt_node_to_map = zx_dt_node_to_map,
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.dt_free_map = pinctrl_utils_free_map,
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.get_groups_count = pinctrl_generic_get_group_count,
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.get_group_name = pinctrl_generic_get_group_name,
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.get_group_pins = pinctrl_generic_get_group_pins,
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};
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#define NONAON_MVAL 2
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static int zx_set_mux(struct pinctrl_dev *pctldev, unsigned int func_selector,
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unsigned int group_selector)
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{
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struct zx_pinctrl *zpctl = pinctrl_dev_get_drvdata(pctldev);
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struct zx_pinctrl_soc_info *info = zpctl->info;
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const struct pinctrl_pin_desc *pindesc = info->pins + group_selector;
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struct zx_pin_data *data = pindesc->drv_data;
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struct zx_mux_desc *mux;
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u32 mask, offset, bitpos;
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struct function_desc *func;
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unsigned long flags;
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u32 val, mval;
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/* Skip reserved pin */
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if (!data)
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return -EINVAL;
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mux = data->muxes;
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mask = (1 << data->width) - 1;
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offset = data->offset;
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bitpos = data->bitpos;
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func = pinmux_generic_get_function(pctldev, func_selector);
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if (!func)
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return -EINVAL;
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while (mux->name) {
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if (strcmp(mux->name, func->name) == 0)
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break;
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mux++;
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}
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/* Found mux value to be written */
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mval = mux->muxval;
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spin_lock_irqsave(&zpctl->lock, flags);
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if (data->aon_pin) {
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/*
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* It's an AON pin, whose mux register offset and bit position
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* can be caluculated from pin number. Each register covers 16
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* pins, and each pin occupies 2 bits.
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*/
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u16 aoffset = pindesc->number / 16 * 4;
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u16 abitpos = (pindesc->number % 16) * 2;
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if (mval & AON_MUX_FLAG) {
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/*
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* This is a mux value that needs to be written into
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* AON pinmux register. Write it and then we're done.
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*/
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val = readl(zpctl->aux_base + aoffset);
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val &= ~(0x3 << abitpos);
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val |= (mval & 0x3) << abitpos;
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writel(val, zpctl->aux_base + aoffset);
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} else {
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/*
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* It's a mux value that needs to be written into TOP
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* pinmux register.
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*/
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val = readl(zpctl->base + offset);
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val &= ~(mask << bitpos);
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val |= (mval & mask) << bitpos;
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writel(val, zpctl->base + offset);
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/*
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* In this case, the AON pinmux register needs to be
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* set up to select non-AON function.
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*/
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val = readl(zpctl->aux_base + aoffset);
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val &= ~(0x3 << abitpos);
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val |= NONAON_MVAL << abitpos;
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writel(val, zpctl->aux_base + aoffset);
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}
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} else {
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/*
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* This is a TOP pin, and we only need to set up TOP pinmux
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* register and then we're done with it.
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*/
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val = readl(zpctl->base + offset);
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val &= ~(mask << bitpos);
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val |= (mval & mask) << bitpos;
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writel(val, zpctl->base + offset);
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}
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spin_unlock_irqrestore(&zpctl->lock, flags);
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return 0;
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}
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static const struct pinmux_ops zx_pinmux_ops = {
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.get_functions_count = pinmux_generic_get_function_count,
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.get_function_name = pinmux_generic_get_function_name,
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.get_function_groups = pinmux_generic_get_function_groups,
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.set_mux = zx_set_mux,
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};
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static int zx_pin_config_get(struct pinctrl_dev *pctldev, unsigned int pin,
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unsigned long *config)
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{
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struct zx_pinctrl *zpctl = pinctrl_dev_get_drvdata(pctldev);
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struct zx_pinctrl_soc_info *info = zpctl->info;
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const struct pinctrl_pin_desc *pindesc = info->pins + pin;
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struct zx_pin_data *data = pindesc->drv_data;
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enum pin_config_param param = pinconf_to_config_param(*config);
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u32 val;
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/* Skip reserved pin */
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if (!data)
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return -EINVAL;
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val = readl(zpctl->aux_base + data->coffset);
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val = val >> data->cbitpos;
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switch (param) {
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case PIN_CONFIG_BIAS_PULL_DOWN:
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val &= ZX_PULL_DOWN;
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val = !!val;
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if (val == 0)
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return -EINVAL;
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break;
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case PIN_CONFIG_BIAS_PULL_UP:
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val &= ZX_PULL_UP;
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val = !!val;
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if (val == 0)
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return -EINVAL;
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break;
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case PIN_CONFIG_INPUT_ENABLE:
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val &= ZX_INPUT_ENABLE;
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val = !!val;
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if (val == 0)
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return -EINVAL;
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break;
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case PIN_CONFIG_DRIVE_STRENGTH:
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val &= ZX_DS_MASK;
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val = val >> ZX_DS_SHIFT;
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break;
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case PIN_CONFIG_SLEW_RATE:
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val &= ZX_SLEW;
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val = !!val;
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break;
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default:
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return -ENOTSUPP;
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}
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*config = pinconf_to_config_packed(param, val);
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return 0;
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}
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static int zx_pin_config_set(struct pinctrl_dev *pctldev, unsigned int pin,
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unsigned long *configs, unsigned int num_configs)
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{
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struct zx_pinctrl *zpctl = pinctrl_dev_get_drvdata(pctldev);
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struct zx_pinctrl_soc_info *info = zpctl->info;
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const struct pinctrl_pin_desc *pindesc = info->pins + pin;
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struct zx_pin_data *data = pindesc->drv_data;
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enum pin_config_param param;
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u32 val, arg;
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int i;
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/* Skip reserved pin */
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if (!data)
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return -EINVAL;
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val = readl(zpctl->aux_base + data->coffset);
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for (i = 0; i < num_configs; i++) {
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param = pinconf_to_config_param(configs[i]);
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arg = pinconf_to_config_argument(configs[i]);
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switch (param) {
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case PIN_CONFIG_BIAS_PULL_DOWN:
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val |= ZX_PULL_DOWN << data->cbitpos;
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break;
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case PIN_CONFIG_BIAS_PULL_UP:
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val |= ZX_PULL_UP << data->cbitpos;
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break;
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case PIN_CONFIG_INPUT_ENABLE:
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val |= ZX_INPUT_ENABLE << data->cbitpos;
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break;
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case PIN_CONFIG_DRIVE_STRENGTH:
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val &= ~(ZX_DS_MASK << data->cbitpos);
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val |= ZX_DS_VALUE(arg) << data->cbitpos;
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break;
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case PIN_CONFIG_SLEW_RATE:
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if (arg)
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val |= ZX_SLEW << data->cbitpos;
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else
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val &= ~ZX_SLEW << data->cbitpos;
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break;
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default:
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return -ENOTSUPP;
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}
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}
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writel(val, zpctl->aux_base + data->coffset);
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return 0;
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}
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static const struct pinconf_ops zx_pinconf_ops = {
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.pin_config_set = zx_pin_config_set,
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.pin_config_get = zx_pin_config_get,
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.is_generic = true,
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};
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static int zx_pinctrl_build_state(struct platform_device *pdev)
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{
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struct zx_pinctrl *zpctl = platform_get_drvdata(pdev);
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struct zx_pinctrl_soc_info *info = zpctl->info;
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struct pinctrl_dev *pctldev = zpctl->pctldev;
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struct function_desc *functions;
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int nfunctions;
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struct group_desc *groups;
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int ngroups;
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int i;
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/* Every single pin composes a group */
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ngroups = info->npins;
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groups = devm_kzalloc(&pdev->dev, ngroups * sizeof(*groups),
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GFP_KERNEL);
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if (!groups)
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return -ENOMEM;
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for (i = 0; i < ngroups; i++) {
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const struct pinctrl_pin_desc *pindesc = info->pins + i;
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struct group_desc *group = groups + i;
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group->name = pindesc->name;
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group->pins = (int *) &pindesc->number;
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group->num_pins = 1;
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radix_tree_insert(&pctldev->pin_group_tree, i, group);
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}
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pctldev->num_groups = ngroups;
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/* Build function list from pin mux functions */
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functions = kcalloc(info->npins, sizeof(*functions), GFP_KERNEL);
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if (!functions)
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return -ENOMEM;
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nfunctions = 0;
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for (i = 0; i < info->npins; i++) {
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const struct pinctrl_pin_desc *pindesc = info->pins + i;
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struct zx_pin_data *data = pindesc->drv_data;
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struct zx_mux_desc *mux;
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/* Reserved pins do not have a drv_data at all */
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if (!data)
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continue;
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/* Loop over all muxes for the pin */
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mux = data->muxes;
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while (mux->name) {
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struct function_desc *func = functions;
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/* Search function list for given mux */
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while (func->name) {
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if (strcmp(mux->name, func->name) == 0) {
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/* Function exists */
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func->num_group_names++;
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break;
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}
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func++;
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}
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if (!func->name) {
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/* New function */
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func->name = mux->name;
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func->num_group_names = 1;
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radix_tree_insert(&pctldev->pin_function_tree,
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nfunctions++, func);
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}
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mux++;
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}
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}
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pctldev->num_functions = nfunctions;
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functions = krealloc(functions, nfunctions * sizeof(*functions),
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GFP_KERNEL);
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/* Find pin groups for every single function */
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for (i = 0; i < info->npins; i++) {
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const struct pinctrl_pin_desc *pindesc = info->pins + i;
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struct zx_pin_data *data = pindesc->drv_data;
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struct zx_mux_desc *mux;
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if (!data)
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continue;
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mux = data->muxes;
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while (mux->name) {
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struct function_desc *func;
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const char **group;
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int j;
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/* Find function for given mux */
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for (j = 0; j < nfunctions; j++)
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if (strcmp(functions[j].name, mux->name) == 0)
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break;
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func = functions + j;
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if (!func->group_names) {
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func->group_names = devm_kzalloc(&pdev->dev,
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func->num_group_names *
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sizeof(*func->group_names),
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GFP_KERNEL);
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if (!func->group_names) {
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kfree(functions);
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return -ENOMEM;
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}
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}
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group = func->group_names;
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while (*group)
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group++;
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*group = pindesc->name;
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mux++;
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}
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}
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return 0;
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}
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int zx_pinctrl_init(struct platform_device *pdev,
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struct zx_pinctrl_soc_info *info)
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{
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struct pinctrl_desc *pctldesc;
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struct zx_pinctrl *zpctl;
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struct device_node *np;
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struct resource *res;
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int ret;
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zpctl = devm_kzalloc(&pdev->dev, sizeof(*zpctl), GFP_KERNEL);
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if (!zpctl)
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return -ENOMEM;
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spin_lock_init(&zpctl->lock);
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res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
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zpctl->base = devm_ioremap_resource(&pdev->dev, res);
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if (IS_ERR(zpctl->base))
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return PTR_ERR(zpctl->base);
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np = of_parse_phandle(pdev->dev.of_node, "zte,auxiliary-controller", 0);
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if (!np) {
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dev_err(&pdev->dev, "failed to find auxiliary controller\n");
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return -ENODEV;
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}
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zpctl->aux_base = of_iomap(np, 0);
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if (!zpctl->aux_base)
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return -ENOMEM;
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zpctl->dev = &pdev->dev;
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zpctl->info = info;
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pctldesc = devm_kzalloc(&pdev->dev, sizeof(*pctldesc), GFP_KERNEL);
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if (!pctldesc)
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return -ENOMEM;
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pctldesc->name = dev_name(&pdev->dev);
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pctldesc->owner = THIS_MODULE;
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pctldesc->pins = info->pins;
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pctldesc->npins = info->npins;
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pctldesc->pctlops = &zx_pinctrl_ops;
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pctldesc->pmxops = &zx_pinmux_ops;
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pctldesc->confops = &zx_pinconf_ops;
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zpctl->pctldev = devm_pinctrl_register(&pdev->dev, pctldesc, zpctl);
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if (IS_ERR(zpctl->pctldev)) {
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ret = PTR_ERR(zpctl->pctldev);
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dev_err(&pdev->dev, "failed to register pinctrl: %d\n", ret);
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return ret;
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}
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platform_set_drvdata(pdev, zpctl);
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ret = zx_pinctrl_build_state(pdev);
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if (ret) {
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dev_err(&pdev->dev, "failed to build state: %d\n", ret);
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return ret;
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}
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dev_info(&pdev->dev, "initialized pinctrl driver\n");
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return 0;
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}
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