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756e46dbaa
The sequence of cpu_enter_lowpower() for Cortex-A15 is different from the sequence for Cortex-A9. This patch implements cpu_enter_lowpower() for EXYNOS5 SoC which has Cortex-A15 cores. Basded on original patch has been submitted by Changhwan Youn Signed-off-by: Changhwan Youn <chaos.youn@samsung.com> Signed-off-by: Abhilash Kesavan <a.kesavan@samsung.com> Cc: Russell King <rmk+kernel@arm.linux.org.uk> [kgene.kim@samsung.com: use flush_cache_louis() instead of flush_cache_all() as per Lorenzo and Santosh's suggestion] Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
161 lines
3.2 KiB
C
161 lines
3.2 KiB
C
/* linux arch/arm/mach-exynos4/hotplug.c
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*
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* Cloned from linux/arch/arm/mach-realview/hotplug.c
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*
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* Copyright (C) 2002 ARM Ltd.
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* All Rights Reserved
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#include <linux/kernel.h>
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#include <linux/errno.h>
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#include <linux/smp.h>
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#include <linux/io.h>
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#include <asm/cacheflush.h>
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#include <asm/cp15.h>
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#include <asm/smp_plat.h>
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#include <mach/regs-pmu.h>
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#include <plat/cpu.h>
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#include "common.h"
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static inline void cpu_enter_lowpower_a9(void)
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{
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unsigned int v;
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flush_cache_all();
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asm volatile(
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" mcr p15, 0, %1, c7, c5, 0\n"
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" mcr p15, 0, %1, c7, c10, 4\n"
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/*
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* Turn off coherency
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*/
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" mrc p15, 0, %0, c1, c0, 1\n"
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" bic %0, %0, %3\n"
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" mcr p15, 0, %0, c1, c0, 1\n"
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" mrc p15, 0, %0, c1, c0, 0\n"
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" bic %0, %0, %2\n"
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" mcr p15, 0, %0, c1, c0, 0\n"
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: "=&r" (v)
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: "r" (0), "Ir" (CR_C), "Ir" (0x40)
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: "cc");
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}
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static inline void cpu_enter_lowpower_a15(void)
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{
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unsigned int v;
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asm volatile(
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" mrc p15, 0, %0, c1, c0, 0\n"
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" bic %0, %0, %1\n"
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" mcr p15, 0, %0, c1, c0, 0\n"
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: "=&r" (v)
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: "Ir" (CR_C)
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: "cc");
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flush_cache_louis();
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asm volatile(
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/*
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* Turn off coherency
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*/
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" mrc p15, 0, %0, c1, c0, 1\n"
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" bic %0, %0, %1\n"
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" mcr p15, 0, %0, c1, c0, 1\n"
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: "=&r" (v)
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: "Ir" (0x40)
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: "cc");
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isb();
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dsb();
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}
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static inline void cpu_leave_lowpower(void)
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{
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unsigned int v;
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asm volatile(
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"mrc p15, 0, %0, c1, c0, 0\n"
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" orr %0, %0, %1\n"
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" mcr p15, 0, %0, c1, c0, 0\n"
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" mrc p15, 0, %0, c1, c0, 1\n"
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" orr %0, %0, %2\n"
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" mcr p15, 0, %0, c1, c0, 1\n"
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: "=&r" (v)
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: "Ir" (CR_C), "Ir" (0x40)
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: "cc");
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}
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static inline void platform_do_lowpower(unsigned int cpu, int *spurious)
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{
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for (;;) {
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/* make cpu1 to be turned off at next WFI command */
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if (cpu == 1)
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__raw_writel(0, S5P_ARM_CORE1_CONFIGURATION);
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/*
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* here's the WFI
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*/
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asm(".word 0xe320f003\n"
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:
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:
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: "memory", "cc");
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if (pen_release == cpu_logical_map(cpu)) {
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/*
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* OK, proper wakeup, we're done
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*/
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break;
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}
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/*
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* Getting here, means that we have come out of WFI without
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* having been woken up - this shouldn't happen
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*
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* Just note it happening - when we're woken, we can report
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* its occurrence.
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*/
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(*spurious)++;
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}
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}
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/*
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* platform-specific code to shutdown a CPU
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*
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* Called with IRQs disabled
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*/
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void __ref exynos_cpu_die(unsigned int cpu)
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{
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int spurious = 0;
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int primary_part = 0;
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/*
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* we're ready for shutdown now, so do it.
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* Exynos4 is A9 based while Exynos5 is A15; check the CPU part
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* number by reading the Main ID register and then perform the
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* appropriate sequence for entering low power.
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*/
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asm("mrc p15, 0, %0, c0, c0, 0" : "=r"(primary_part) : : "cc");
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if ((primary_part & 0xfff0) == 0xc0f0)
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cpu_enter_lowpower_a15();
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else
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cpu_enter_lowpower_a9();
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platform_do_lowpower(cpu, &spurious);
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/*
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* bring this CPU back into the world of cache
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* coherency, and then restore interrupts
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*/
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cpu_leave_lowpower();
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if (spurious)
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pr_warn("CPU%u: %u spurious wakeup calls\n", cpu, spurious);
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}
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