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https://github.com/edk2-porting/linux-next.git
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a8c21a5451
This adds the etnaviv DRM driver and hooks it up in Makefiles and Kconfig. Signed-off-by: Christian Gmeiner <christian.gmeiner@gmail.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk> Signed-off-by: Lucas Stach <l.stach@pengutronix.de> Acked-by: Daniel Vetter <daniel.vetter@ffwll.ch>
269 lines
7.1 KiB
C
269 lines
7.1 KiB
C
/*
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* Copyright (C) 2014 Etnaviv Project
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* Author: Christian Gmeiner <christian.gmeiner@gmail.com>
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License version 2 as published by
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* the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License along with
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* this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#include "etnaviv_gpu.h"
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#include "etnaviv_gem.h"
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#include "etnaviv_mmu.h"
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#include "common.xml.h"
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#include "state.xml.h"
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#include "cmdstream.xml.h"
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/*
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* Command Buffer helper:
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*/
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static inline void OUT(struct etnaviv_cmdbuf *buffer, u32 data)
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{
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u32 *vaddr = (u32 *)buffer->vaddr;
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BUG_ON(buffer->user_size >= buffer->size);
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vaddr[buffer->user_size / 4] = data;
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buffer->user_size += 4;
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}
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static inline void CMD_LOAD_STATE(struct etnaviv_cmdbuf *buffer,
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u32 reg, u32 value)
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{
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u32 index = reg >> VIV_FE_LOAD_STATE_HEADER_OFFSET__SHR;
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buffer->user_size = ALIGN(buffer->user_size, 8);
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/* write a register via cmd stream */
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OUT(buffer, VIV_FE_LOAD_STATE_HEADER_OP_LOAD_STATE |
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VIV_FE_LOAD_STATE_HEADER_COUNT(1) |
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VIV_FE_LOAD_STATE_HEADER_OFFSET(index));
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OUT(buffer, value);
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}
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static inline void CMD_END(struct etnaviv_cmdbuf *buffer)
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{
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buffer->user_size = ALIGN(buffer->user_size, 8);
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OUT(buffer, VIV_FE_END_HEADER_OP_END);
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}
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static inline void CMD_WAIT(struct etnaviv_cmdbuf *buffer)
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{
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buffer->user_size = ALIGN(buffer->user_size, 8);
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OUT(buffer, VIV_FE_WAIT_HEADER_OP_WAIT | 200);
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}
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static inline void CMD_LINK(struct etnaviv_cmdbuf *buffer,
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u16 prefetch, u32 address)
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{
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buffer->user_size = ALIGN(buffer->user_size, 8);
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OUT(buffer, VIV_FE_LINK_HEADER_OP_LINK |
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VIV_FE_LINK_HEADER_PREFETCH(prefetch));
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OUT(buffer, address);
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}
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static inline void CMD_STALL(struct etnaviv_cmdbuf *buffer,
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u32 from, u32 to)
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{
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buffer->user_size = ALIGN(buffer->user_size, 8);
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OUT(buffer, VIV_FE_STALL_HEADER_OP_STALL);
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OUT(buffer, VIV_FE_STALL_TOKEN_FROM(from) | VIV_FE_STALL_TOKEN_TO(to));
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}
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static void etnaviv_cmd_select_pipe(struct etnaviv_cmdbuf *buffer, u8 pipe)
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{
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u32 flush;
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u32 stall;
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/*
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* This assumes that if we're switching to 2D, we're switching
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* away from 3D, and vice versa. Hence, if we're switching to
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* the 2D core, we need to flush the 3D depth and color caches,
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* otherwise we need to flush the 2D pixel engine cache.
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*/
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if (pipe == ETNA_PIPE_2D)
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flush = VIVS_GL_FLUSH_CACHE_DEPTH | VIVS_GL_FLUSH_CACHE_COLOR;
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else
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flush = VIVS_GL_FLUSH_CACHE_PE2D;
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stall = VIVS_GL_SEMAPHORE_TOKEN_FROM(SYNC_RECIPIENT_FE) |
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VIVS_GL_SEMAPHORE_TOKEN_TO(SYNC_RECIPIENT_PE);
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CMD_LOAD_STATE(buffer, VIVS_GL_FLUSH_CACHE, flush);
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CMD_LOAD_STATE(buffer, VIVS_GL_SEMAPHORE_TOKEN, stall);
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CMD_STALL(buffer, SYNC_RECIPIENT_FE, SYNC_RECIPIENT_PE);
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CMD_LOAD_STATE(buffer, VIVS_GL_PIPE_SELECT,
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VIVS_GL_PIPE_SELECT_PIPE(pipe));
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}
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static u32 gpu_va(struct etnaviv_gpu *gpu, struct etnaviv_cmdbuf *buf)
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{
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return buf->paddr - gpu->memory_base;
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}
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static void etnaviv_buffer_dump(struct etnaviv_gpu *gpu,
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struct etnaviv_cmdbuf *buf, u32 off, u32 len)
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{
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u32 size = buf->size;
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u32 *ptr = buf->vaddr + off;
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dev_info(gpu->dev, "virt %p phys 0x%08x free 0x%08x\n",
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ptr, gpu_va(gpu, buf) + off, size - len * 4 - off);
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print_hex_dump(KERN_INFO, "cmd ", DUMP_PREFIX_OFFSET, 16, 4,
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ptr, len * 4, 0);
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}
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u16 etnaviv_buffer_init(struct etnaviv_gpu *gpu)
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{
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struct etnaviv_cmdbuf *buffer = gpu->buffer;
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/* initialize buffer */
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buffer->user_size = 0;
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CMD_WAIT(buffer);
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CMD_LINK(buffer, 2, gpu_va(gpu, buffer) + buffer->user_size - 4);
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return buffer->user_size / 8;
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}
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void etnaviv_buffer_end(struct etnaviv_gpu *gpu)
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{
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struct etnaviv_cmdbuf *buffer = gpu->buffer;
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/* Replace the last WAIT with an END */
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buffer->user_size -= 16;
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CMD_END(buffer);
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mb();
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}
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void etnaviv_buffer_queue(struct etnaviv_gpu *gpu, unsigned int event,
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struct etnaviv_cmdbuf *cmdbuf)
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{
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struct etnaviv_cmdbuf *buffer = gpu->buffer;
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u32 *lw = buffer->vaddr + buffer->user_size - 16;
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u32 back, link_target, link_size, reserve_size, extra_size = 0;
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if (drm_debug & DRM_UT_DRIVER)
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etnaviv_buffer_dump(gpu, buffer, 0, 0x50);
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/*
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* If we need to flush the MMU prior to submitting this buffer, we
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* will need to append a mmu flush load state, followed by a new
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* link to this buffer - a total of four additional words.
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*/
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if (gpu->mmu->need_flush || gpu->switch_context) {
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/* link command */
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extra_size += 2;
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/* flush command */
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if (gpu->mmu->need_flush)
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extra_size += 2;
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/* pipe switch commands */
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if (gpu->switch_context)
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extra_size += 8;
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}
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reserve_size = (6 + extra_size) * 4;
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/*
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* if we are going to completely overflow the buffer, we need to wrap.
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*/
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if (buffer->user_size + reserve_size > buffer->size)
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buffer->user_size = 0;
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/* save offset back into main buffer */
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back = buffer->user_size + reserve_size - 6 * 4;
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link_target = gpu_va(gpu, buffer) + buffer->user_size;
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link_size = 6;
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/* Skip over any extra instructions */
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link_target += extra_size * sizeof(u32);
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if (drm_debug & DRM_UT_DRIVER)
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pr_info("stream link to 0x%08x @ 0x%08x %p\n",
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link_target, gpu_va(gpu, cmdbuf), cmdbuf->vaddr);
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/* jump back from cmd to main buffer */
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CMD_LINK(cmdbuf, link_size, link_target);
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link_target = gpu_va(gpu, cmdbuf);
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link_size = cmdbuf->size / 8;
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if (drm_debug & DRM_UT_DRIVER) {
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print_hex_dump(KERN_INFO, "cmd ", DUMP_PREFIX_OFFSET, 16, 4,
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cmdbuf->vaddr, cmdbuf->size, 0);
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pr_info("link op: %p\n", lw);
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pr_info("link addr: %p\n", lw + 1);
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pr_info("addr: 0x%08x\n", link_target);
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pr_info("back: 0x%08x\n", gpu_va(gpu, buffer) + back);
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pr_info("event: %d\n", event);
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}
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if (gpu->mmu->need_flush || gpu->switch_context) {
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u32 new_target = gpu_va(gpu, buffer) + buffer->user_size;
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if (gpu->mmu->need_flush) {
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/* Add the MMU flush */
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CMD_LOAD_STATE(buffer, VIVS_GL_FLUSH_MMU,
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VIVS_GL_FLUSH_MMU_FLUSH_FEMMU |
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VIVS_GL_FLUSH_MMU_FLUSH_UNK1 |
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VIVS_GL_FLUSH_MMU_FLUSH_UNK2 |
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VIVS_GL_FLUSH_MMU_FLUSH_PEMMU |
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VIVS_GL_FLUSH_MMU_FLUSH_UNK4);
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gpu->mmu->need_flush = false;
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}
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if (gpu->switch_context) {
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etnaviv_cmd_select_pipe(buffer, cmdbuf->exec_state);
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gpu->switch_context = false;
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}
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/* And the link to the first buffer */
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CMD_LINK(buffer, link_size, link_target);
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/* Update the link target to point to above instructions */
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link_target = new_target;
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link_size = extra_size;
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}
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/* trigger event */
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CMD_LOAD_STATE(buffer, VIVS_GL_EVENT, VIVS_GL_EVENT_EVENT_ID(event) |
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VIVS_GL_EVENT_FROM_PE);
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/* append WAIT/LINK to main buffer */
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CMD_WAIT(buffer);
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CMD_LINK(buffer, 2, gpu_va(gpu, buffer) + (buffer->user_size - 4));
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/* Change WAIT into a LINK command; write the address first. */
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*(lw + 1) = link_target;
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mb();
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*(lw) = VIV_FE_LINK_HEADER_OP_LINK |
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VIV_FE_LINK_HEADER_PREFETCH(link_size);
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mb();
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if (drm_debug & DRM_UT_DRIVER)
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etnaviv_buffer_dump(gpu, buffer, 0, 0x50);
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}
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