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7120438e5d
Convert fsl_rstcr_restart into a function to be registered with register_reset_handler(). Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com> [scottwood: Converted mvme7100 as well] Signed-off-by: Scott Wood <oss@buserror.net>
109 lines
2.5 KiB
C
109 lines
2.5 KiB
C
/*
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* Based on MPC8560 ADS and arch/ppc stx_gp3 ports
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*
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* Maintained by Kumar Gala (see MAINTAINERS for contact information)
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*
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* Copyright 2008 Freescale Semiconductor Inc.
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*
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* Dan Malek <dan@embeddededge.com>
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* Copyright 2004 Embedded Edge, LLC
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*
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* Copied from mpc8560_ads.c
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* Copyright 2002, 2003 Motorola Inc.
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*
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* Ported to 2.6, Matt Porter <mporter@kernel.crashing.org>
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* Copyright 2004-2005 MontaVista Software, Inc.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License as published by the
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* Free Software Foundation; either version 2 of the License, or (at your
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* option) any later version.
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*/
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#include <linux/stddef.h>
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#include <linux/kernel.h>
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#include <linux/pci.h>
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#include <linux/kdev_t.h>
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#include <linux/delay.h>
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#include <linux/seq_file.h>
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#include <linux/of_platform.h>
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#include <asm/time.h>
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#include <asm/machdep.h>
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#include <asm/pci-bridge.h>
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#include <asm/mpic.h>
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#include <asm/prom.h>
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#include <mm/mmu_decl.h>
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#include <asm/udbg.h>
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#include <sysdev/fsl_soc.h>
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#include <sysdev/fsl_pci.h>
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#include "mpc85xx.h"
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#ifdef CONFIG_CPM2
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#include <asm/cpm2.h>
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#endif /* CONFIG_CPM2 */
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static void __init stx_gp3_pic_init(void)
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{
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struct mpic *mpic = mpic_alloc(NULL, 0, MPIC_BIG_ENDIAN,
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0, 256, " OpenPIC ");
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BUG_ON(mpic == NULL);
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mpic_init(mpic);
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mpc85xx_cpm2_pic_init();
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}
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/*
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* Setup the architecture
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*/
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static void __init stx_gp3_setup_arch(void)
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{
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if (ppc_md.progress)
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ppc_md.progress("stx_gp3_setup_arch()", 0);
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fsl_pci_assign_primary();
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#ifdef CONFIG_CPM2
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cpm2_reset();
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#endif
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}
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static void stx_gp3_show_cpuinfo(struct seq_file *m)
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{
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uint pvid, svid, phid1;
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pvid = mfspr(SPRN_PVR);
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svid = mfspr(SPRN_SVR);
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seq_printf(m, "Vendor\t\t: RPC Electronics STx\n");
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seq_printf(m, "PVR\t\t: 0x%x\n", pvid);
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seq_printf(m, "SVR\t\t: 0x%x\n", svid);
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/* Display cpu Pll setting */
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phid1 = mfspr(SPRN_HID1);
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seq_printf(m, "PLL setting\t: 0x%x\n", ((phid1 >> 24) & 0x3f));
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}
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machine_arch_initcall(stx_gp3, mpc85xx_common_publish_devices);
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/*
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* Called very early, device-tree isn't unflattened
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*/
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static int __init stx_gp3_probe(void)
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{
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return of_machine_is_compatible("stx,gp3-8560");
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}
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define_machine(stx_gp3) {
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.name = "STX GP3",
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.probe = stx_gp3_probe,
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.setup_arch = stx_gp3_setup_arch,
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.init_IRQ = stx_gp3_pic_init,
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.show_cpuinfo = stx_gp3_show_cpuinfo,
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.get_irq = mpic_get_irq,
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.calibrate_decr = generic_calibrate_decr,
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.progress = udbg_progress,
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};
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