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Initial git repository build. I'm not bothering with the full history, even though we have it. We can create a separate "historical" git archive of that later if we want to, and in the meantime it's about 3.2GB when imported into git - space that would just make the early git days unnecessarily complicated, when we don't have a lot of good infrastructure for it. Let it rip!
70 lines
2.5 KiB
Plaintext
70 lines
2.5 KiB
Plaintext
IRQ affinity on IA64 platforms
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------------------------------
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07.01.2002, Erich Focht <efocht@ess.nec.de>
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By writing to /proc/irq/IRQ#/smp_affinity the interrupt routing can be
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controlled. The behavior on IA64 platforms is slightly different from
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that described in Documentation/IRQ-affinity.txt for i386 systems.
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Because of the usage of SAPIC mode and physical destination mode the
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IRQ target is one particular CPU and cannot be a mask of several
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CPUs. Only the first non-zero bit is taken into account.
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Usage examples:
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The target CPU has to be specified as a hexadecimal CPU mask. The
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first non-zero bit is the selected CPU. This format has been kept for
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compatibility reasons with i386.
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Set the delivery mode of interrupt 41 to fixed and route the
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interrupts to CPU #3 (logical CPU number) (2^3=0x08):
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echo "8" >/proc/irq/41/smp_affinity
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Set the default route for IRQ number 41 to CPU 6 in lowest priority
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delivery mode (redirectable):
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echo "r 40" >/proc/irq/41/smp_affinity
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The output of the command
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cat /proc/irq/IRQ#/smp_affinity
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gives the target CPU mask for the specified interrupt vector. If the CPU
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mask is preceded by the character "r", the interrupt is redirectable
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(i.e. lowest priority mode routing is used), otherwise its route is
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fixed.
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Initialization and default behavior:
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If the platform features IRQ redirection (info provided by SAL) all
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IO-SAPIC interrupts are initialized with CPU#0 as their default target
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and the routing is the so called "lowest priority mode" (actually
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fixed SAPIC mode with hint). The XTP chipset registers are used as hints
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for the IRQ routing. Currently in Linux XTP registers can have three
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values:
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- minimal for an idle task,
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- normal if any other task runs,
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- maximal if the CPU is going to be switched off.
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The IRQ is routed to the CPU with lowest XTP register value, the
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search begins at the default CPU. Therefore most of the interrupts
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will be handled by CPU #0.
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If the platform doesn't feature interrupt redirection IOSAPIC fixed
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routing is used. The target CPUs are distributed in a round robin
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manner. IRQs will be routed only to the selected target CPUs. Check
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with
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cat /proc/interrupts
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Comments:
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On large (multi-node) systems it is recommended to route the IRQs to
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the node to which the corresponding device is connected.
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For systems like the NEC AzusA we get IRQ node-affinity for free. This
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is because usually the chipsets on each node redirect the interrupts
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only to their own CPUs (as they cannot see the XTP registers on the
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other nodes).
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