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fea80311a9
When CONFIG_PCI is not enabled, CONFIG_EISA=y, and CONFIG_GENERIC_IOMAP=y, drivers/net/3c59x.c build fails due to a recent small change to <asm-generic/iomap.h> that surrounds pci_iomap() and pci_iounmap() with #ifdef CONFIG_PCI/#endif. Since that patch to iomap.h looks correct, add stubs for pci_iomap() and pci_iounmap() with CONFIG_PCI is not enabled to fix the build errors. drivers/net/3c59x.c:1026: error: implicit declaration of function 'pci_iomap' drivers/net/3c59x.c:1038: error: implicit declaration of function 'pci_iounmap' Signed-off-by: Randy Dunlap <rdunlap@xenotime.net> Cc: Jonas Bonn <jonas@southpole.se> Cc: Arnd Bergmann <arnd@arndb.de> Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
85 lines
2.9 KiB
C
85 lines
2.9 KiB
C
#ifndef __GENERIC_IO_H
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#define __GENERIC_IO_H
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#include <linux/linkage.h>
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#include <asm/byteorder.h>
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/*
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* These are the "generic" interfaces for doing new-style
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* memory-mapped or PIO accesses. Architectures may do
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* their own arch-optimized versions, these just act as
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* wrappers around the old-style IO register access functions:
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* read[bwl]/write[bwl]/in[bwl]/out[bwl]
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*
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* Don't include this directly, include it from <asm/io.h>.
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*/
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/*
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* Read/write from/to an (offsettable) iomem cookie. It might be a PIO
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* access or a MMIO access, these functions don't care. The info is
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* encoded in the hardware mapping set up by the mapping functions
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* (or the cookie itself, depending on implementation and hw).
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*
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* The generic routines just encode the PIO/MMIO as part of the
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* cookie, and coldly assume that the MMIO IO mappings are not
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* in the low address range. Architectures for which this is not
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* true can't use this generic implementation.
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*/
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extern unsigned int ioread8(void __iomem *);
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extern unsigned int ioread16(void __iomem *);
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extern unsigned int ioread16be(void __iomem *);
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extern unsigned int ioread32(void __iomem *);
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extern unsigned int ioread32be(void __iomem *);
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extern void iowrite8(u8, void __iomem *);
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extern void iowrite16(u16, void __iomem *);
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extern void iowrite16be(u16, void __iomem *);
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extern void iowrite32(u32, void __iomem *);
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extern void iowrite32be(u32, void __iomem *);
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/*
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* "string" versions of the above. Note that they
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* use native byte ordering for the accesses (on
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* the assumption that IO and memory agree on a
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* byte order, and CPU byteorder is irrelevant).
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*
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* They do _not_ update the port address. If you
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* want MMIO that copies stuff laid out in MMIO
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* memory across multiple ports, use "memcpy_toio()"
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* and friends.
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*/
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extern void ioread8_rep(void __iomem *port, void *buf, unsigned long count);
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extern void ioread16_rep(void __iomem *port, void *buf, unsigned long count);
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extern void ioread32_rep(void __iomem *port, void *buf, unsigned long count);
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extern void iowrite8_rep(void __iomem *port, const void *buf, unsigned long count);
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extern void iowrite16_rep(void __iomem *port, const void *buf, unsigned long count);
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extern void iowrite32_rep(void __iomem *port, const void *buf, unsigned long count);
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#ifdef CONFIG_HAS_IOPORT
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/* Create a virtual mapping cookie for an IO port range */
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extern void __iomem *ioport_map(unsigned long port, unsigned int nr);
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extern void ioport_unmap(void __iomem *);
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#endif
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#ifndef ARCH_HAS_IOREMAP_WC
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#define ioremap_wc ioremap_nocache
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#endif
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#ifdef CONFIG_PCI
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/* Create a virtual mapping cookie for a PCI BAR (memory or IO) */
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struct pci_dev;
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extern void __iomem *pci_iomap(struct pci_dev *dev, int bar, unsigned long max);
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extern void pci_iounmap(struct pci_dev *dev, void __iomem *);
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#else
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struct pci_dev;
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static inline void __iomem *pci_iomap(struct pci_dev *dev, int bar, unsigned long max)
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{
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return NULL;
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}
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static inline void pci_iounmap(struct pci_dev *dev, void __iomem *addr)
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{ }
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#endif
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#endif
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