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347 lines
8.3 KiB
C
347 lines
8.3 KiB
C
/*
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* arch/arm/mm/cache-l2x0.c - L210/L220 cache controller support
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*
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* Copyright (C) 2007 ARM Limited
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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*/
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#include <linux/init.h>
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#include <linux/spinlock.h>
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#include <linux/io.h>
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#include <asm/cacheflush.h>
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#include <asm/hardware/cache-l2x0.h>
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#define CACHE_LINE_SIZE 32
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static void __iomem *l2x0_base;
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static DEFINE_SPINLOCK(l2x0_lock);
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static uint32_t l2x0_way_mask; /* Bitmask of active ways */
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static uint32_t l2x0_size;
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static inline void cache_wait_way(void __iomem *reg, unsigned long mask)
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{
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/* wait for cache operation by line or way to complete */
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while (readl_relaxed(reg) & mask)
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;
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}
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#ifdef CONFIG_CACHE_PL310
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static inline void cache_wait(void __iomem *reg, unsigned long mask)
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{
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/* cache operations by line are atomic on PL310 */
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}
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#else
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#define cache_wait cache_wait_way
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#endif
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static inline void cache_sync(void)
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{
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void __iomem *base = l2x0_base;
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#ifdef CONFIG_ARM_ERRATA_753970
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/* write to an unmmapped register */
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writel_relaxed(0, base + L2X0_DUMMY_REG);
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#else
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writel_relaxed(0, base + L2X0_CACHE_SYNC);
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#endif
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cache_wait(base + L2X0_CACHE_SYNC, 1);
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}
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static inline void l2x0_clean_line(unsigned long addr)
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{
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void __iomem *base = l2x0_base;
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cache_wait(base + L2X0_CLEAN_LINE_PA, 1);
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writel_relaxed(addr, base + L2X0_CLEAN_LINE_PA);
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}
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static inline void l2x0_inv_line(unsigned long addr)
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{
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void __iomem *base = l2x0_base;
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cache_wait(base + L2X0_INV_LINE_PA, 1);
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writel_relaxed(addr, base + L2X0_INV_LINE_PA);
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}
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#if defined(CONFIG_PL310_ERRATA_588369) || defined(CONFIG_PL310_ERRATA_727915)
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#define debug_writel(val) outer_cache.set_debug(val)
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static void l2x0_set_debug(unsigned long val)
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{
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writel_relaxed(val, l2x0_base + L2X0_DEBUG_CTRL);
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}
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#else
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/* Optimised out for non-errata case */
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static inline void debug_writel(unsigned long val)
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{
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}
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#define l2x0_set_debug NULL
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#endif
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#ifdef CONFIG_PL310_ERRATA_588369
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static inline void l2x0_flush_line(unsigned long addr)
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{
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void __iomem *base = l2x0_base;
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/* Clean by PA followed by Invalidate by PA */
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cache_wait(base + L2X0_CLEAN_LINE_PA, 1);
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writel_relaxed(addr, base + L2X0_CLEAN_LINE_PA);
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cache_wait(base + L2X0_INV_LINE_PA, 1);
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writel_relaxed(addr, base + L2X0_INV_LINE_PA);
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}
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#else
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static inline void l2x0_flush_line(unsigned long addr)
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{
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void __iomem *base = l2x0_base;
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cache_wait(base + L2X0_CLEAN_INV_LINE_PA, 1);
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writel_relaxed(addr, base + L2X0_CLEAN_INV_LINE_PA);
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}
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#endif
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static void l2x0_cache_sync(void)
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{
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unsigned long flags;
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spin_lock_irqsave(&l2x0_lock, flags);
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cache_sync();
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spin_unlock_irqrestore(&l2x0_lock, flags);
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}
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static void l2x0_flush_all(void)
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{
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unsigned long flags;
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/* clean all ways */
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spin_lock_irqsave(&l2x0_lock, flags);
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debug_writel(0x03);
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writel_relaxed(l2x0_way_mask, l2x0_base + L2X0_CLEAN_INV_WAY);
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cache_wait_way(l2x0_base + L2X0_CLEAN_INV_WAY, l2x0_way_mask);
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cache_sync();
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debug_writel(0x00);
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spin_unlock_irqrestore(&l2x0_lock, flags);
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}
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static void l2x0_clean_all(void)
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{
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unsigned long flags;
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/* clean all ways */
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spin_lock_irqsave(&l2x0_lock, flags);
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writel_relaxed(l2x0_way_mask, l2x0_base + L2X0_CLEAN_WAY);
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cache_wait_way(l2x0_base + L2X0_CLEAN_WAY, l2x0_way_mask);
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cache_sync();
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spin_unlock_irqrestore(&l2x0_lock, flags);
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}
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static void l2x0_inv_all(void)
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{
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unsigned long flags;
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/* invalidate all ways */
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spin_lock_irqsave(&l2x0_lock, flags);
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/* Invalidating when L2 is enabled is a nono */
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BUG_ON(readl(l2x0_base + L2X0_CTRL) & 1);
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writel_relaxed(l2x0_way_mask, l2x0_base + L2X0_INV_WAY);
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cache_wait_way(l2x0_base + L2X0_INV_WAY, l2x0_way_mask);
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cache_sync();
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spin_unlock_irqrestore(&l2x0_lock, flags);
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}
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static void l2x0_inv_range(unsigned long start, unsigned long end)
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{
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void __iomem *base = l2x0_base;
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unsigned long flags;
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spin_lock_irqsave(&l2x0_lock, flags);
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if (start & (CACHE_LINE_SIZE - 1)) {
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start &= ~(CACHE_LINE_SIZE - 1);
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debug_writel(0x03);
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l2x0_flush_line(start);
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debug_writel(0x00);
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start += CACHE_LINE_SIZE;
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}
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if (end & (CACHE_LINE_SIZE - 1)) {
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end &= ~(CACHE_LINE_SIZE - 1);
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debug_writel(0x03);
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l2x0_flush_line(end);
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debug_writel(0x00);
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}
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while (start < end) {
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unsigned long blk_end = start + min(end - start, 4096UL);
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while (start < blk_end) {
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l2x0_inv_line(start);
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start += CACHE_LINE_SIZE;
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}
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if (blk_end < end) {
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spin_unlock_irqrestore(&l2x0_lock, flags);
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spin_lock_irqsave(&l2x0_lock, flags);
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}
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}
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cache_wait(base + L2X0_INV_LINE_PA, 1);
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cache_sync();
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spin_unlock_irqrestore(&l2x0_lock, flags);
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}
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static void l2x0_clean_range(unsigned long start, unsigned long end)
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{
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void __iomem *base = l2x0_base;
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unsigned long flags;
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if ((end - start) >= l2x0_size) {
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l2x0_clean_all();
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return;
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}
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spin_lock_irqsave(&l2x0_lock, flags);
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start &= ~(CACHE_LINE_SIZE - 1);
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while (start < end) {
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unsigned long blk_end = start + min(end - start, 4096UL);
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while (start < blk_end) {
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l2x0_clean_line(start);
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start += CACHE_LINE_SIZE;
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}
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if (blk_end < end) {
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spin_unlock_irqrestore(&l2x0_lock, flags);
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spin_lock_irqsave(&l2x0_lock, flags);
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}
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}
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cache_wait(base + L2X0_CLEAN_LINE_PA, 1);
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cache_sync();
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spin_unlock_irqrestore(&l2x0_lock, flags);
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}
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static void l2x0_flush_range(unsigned long start, unsigned long end)
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{
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void __iomem *base = l2x0_base;
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unsigned long flags;
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if ((end - start) >= l2x0_size) {
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l2x0_flush_all();
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return;
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}
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spin_lock_irqsave(&l2x0_lock, flags);
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start &= ~(CACHE_LINE_SIZE - 1);
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while (start < end) {
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unsigned long blk_end = start + min(end - start, 4096UL);
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debug_writel(0x03);
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while (start < blk_end) {
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l2x0_flush_line(start);
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start += CACHE_LINE_SIZE;
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}
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debug_writel(0x00);
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if (blk_end < end) {
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spin_unlock_irqrestore(&l2x0_lock, flags);
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spin_lock_irqsave(&l2x0_lock, flags);
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}
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}
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cache_wait(base + L2X0_CLEAN_INV_LINE_PA, 1);
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cache_sync();
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spin_unlock_irqrestore(&l2x0_lock, flags);
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}
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static void l2x0_disable(void)
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{
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unsigned long flags;
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spin_lock_irqsave(&l2x0_lock, flags);
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writel(0, l2x0_base + L2X0_CTRL);
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spin_unlock_irqrestore(&l2x0_lock, flags);
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}
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void __init l2x0_init(void __iomem *base, __u32 aux_val, __u32 aux_mask)
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{
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__u32 aux;
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__u32 cache_id;
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__u32 way_size = 0;
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int ways;
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const char *type;
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l2x0_base = base;
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cache_id = readl_relaxed(l2x0_base + L2X0_CACHE_ID);
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aux = readl_relaxed(l2x0_base + L2X0_AUX_CTRL);
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aux &= aux_mask;
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aux |= aux_val;
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/* Determine the number of ways */
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switch (cache_id & L2X0_CACHE_ID_PART_MASK) {
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case L2X0_CACHE_ID_PART_L310:
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if (aux & (1 << 16))
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ways = 16;
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else
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ways = 8;
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type = "L310";
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break;
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case L2X0_CACHE_ID_PART_L210:
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ways = (aux >> 13) & 0xf;
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type = "L210";
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break;
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default:
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/* Assume unknown chips have 8 ways */
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ways = 8;
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type = "L2x0 series";
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break;
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}
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l2x0_way_mask = (1 << ways) - 1;
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/*
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* L2 cache Size = Way size * Number of ways
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*/
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way_size = (aux & L2X0_AUX_CTRL_WAY_SIZE_MASK) >> 17;
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way_size = 1 << (way_size + 3);
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l2x0_size = ways * way_size * SZ_1K;
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/*
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* Check if l2x0 controller is already enabled.
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* If you are booting from non-secure mode
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* accessing the below registers will fault.
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*/
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if (!(readl_relaxed(l2x0_base + L2X0_CTRL) & 1)) {
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/* l2x0 controller is disabled */
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writel_relaxed(aux, l2x0_base + L2X0_AUX_CTRL);
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l2x0_inv_all();
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/* enable L2X0 */
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writel_relaxed(1, l2x0_base + L2X0_CTRL);
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}
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outer_cache.inv_range = l2x0_inv_range;
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outer_cache.clean_range = l2x0_clean_range;
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outer_cache.flush_range = l2x0_flush_range;
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outer_cache.sync = l2x0_cache_sync;
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outer_cache.flush_all = l2x0_flush_all;
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outer_cache.inv_all = l2x0_inv_all;
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outer_cache.disable = l2x0_disable;
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outer_cache.set_debug = l2x0_set_debug;
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printk(KERN_INFO "%s cache controller enabled\n", type);
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printk(KERN_INFO "l2x0: %d ways, CACHE_ID 0x%08x, AUX_CTRL 0x%08x, Cache size: %d B\n",
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ways, cache_id, aux, l2x0_size);
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}
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