Atish Patra 31738ede9b RISC-V: Issue a local tlbflush if possible. ... In RISC-V, tlb flush happens via SBI which is expensive. If the local cpu is the only cpu in cpumask, there is no need to invoke a SBI call. Just do a local flush and return. Signed-off-by: Atish Patra <atish.patra@wdc.com> Reviewed-by: Christoph Hellwig <hch@lst.de> Signed-off-by: Paul Walmsley <paul.walmsley@sifive.com>		2019-10-29 11:32:18 -07:00
..
cacheflush.c	riscv: cleanup riscv_cpuid_to_hartid_mask	2019-09-05 01:51:57 -07:00
context.c	riscv: add missing header file includes	2019-10-28 00:46:01 -07:00
extable.c	treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 120	2019-05-24 17:39:02 +02:00
fault.c	riscv: add prototypes for assembly language functions from head.S	2019-10-28 00:46:00 -07:00
hugetlbpage.c	riscv: Introduce huge page support for 32/64bit kernel	2019-07-03 15:23:38 -07:00
init.c	riscv: init: merge split string literals in preprocessor directive	2019-10-28 00:46:01 -07:00
ioremap.c	treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 286	2019-06-05 17:36:37 +02:00
Makefile	riscv: move the TLB flush logic out of line	2019-09-05 01:54:51 -07:00
sifive_l2_cache.c	riscv: mark some code and data as file-static	2019-10-28 00:46:01 -07:00
tlbflush.c	RISC-V: Issue a local tlbflush if possible.	2019-10-29 11:32:18 -07:00