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7034228792
Having received another series of whitespace patches I decided to do this once and for all rather than dealing with this kind of patches trickling in forever. Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
137 lines
3.4 KiB
C
137 lines
3.4 KiB
C
/*
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* Atheros DB120 reference board support
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*
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* Copyright (c) 2011 Qualcomm Atheros
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* Copyright (c) 2011 Gabor Juhos <juhosg@openwrt.org>
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*
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* Permission to use, copy, modify, and/or distribute this software for any
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* purpose with or without fee is hereby granted, provided that the above
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* copyright notice and this permission notice appear in all copies.
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*
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* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
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* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
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* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
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* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
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* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
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* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
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*
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*/
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#include <linux/pci.h>
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#include <linux/ath9k_platform.h>
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#include "machtypes.h"
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#include "dev-gpio-buttons.h"
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#include "dev-leds-gpio.h"
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#include "dev-spi.h"
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#include "dev-usb.h"
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#include "dev-wmac.h"
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#include "pci.h"
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#define DB120_GPIO_LED_WLAN_5G 12
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#define DB120_GPIO_LED_WLAN_2G 13
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#define DB120_GPIO_LED_STATUS 14
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#define DB120_GPIO_LED_WPS 15
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#define DB120_GPIO_BTN_WPS 16
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#define DB120_KEYS_POLL_INTERVAL 20 /* msecs */
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#define DB120_KEYS_DEBOUNCE_INTERVAL (3 * DB120_KEYS_POLL_INTERVAL)
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#define DB120_WMAC_CALDATA_OFFSET 0x1000
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#define DB120_PCIE_CALDATA_OFFSET 0x5000
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static struct gpio_led db120_leds_gpio[] __initdata = {
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{
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.name = "db120:green:status",
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.gpio = DB120_GPIO_LED_STATUS,
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.active_low = 1,
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},
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{
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.name = "db120:green:wps",
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.gpio = DB120_GPIO_LED_WPS,
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.active_low = 1,
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},
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{
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.name = "db120:green:wlan-5g",
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.gpio = DB120_GPIO_LED_WLAN_5G,
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.active_low = 1,
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},
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{
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.name = "db120:green:wlan-2g",
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.gpio = DB120_GPIO_LED_WLAN_2G,
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.active_low = 1,
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},
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};
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static struct gpio_keys_button db120_gpio_keys[] __initdata = {
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{
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.desc = "WPS button",
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.type = EV_KEY,
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.code = KEY_WPS_BUTTON,
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.debounce_interval = DB120_KEYS_DEBOUNCE_INTERVAL,
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.gpio = DB120_GPIO_BTN_WPS,
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.active_low = 1,
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},
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};
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static struct spi_board_info db120_spi_info[] = {
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{
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.bus_num = 0,
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.chip_select = 0,
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.max_speed_hz = 25000000,
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.modalias = "s25sl064a",
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}
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};
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static struct ath79_spi_platform_data db120_spi_data = {
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.bus_num = 0,
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.num_chipselect = 1,
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};
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#ifdef CONFIG_PCI
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static struct ath9k_platform_data db120_ath9k_data;
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static int db120_pci_plat_dev_init(struct pci_dev *dev)
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{
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switch (PCI_SLOT(dev->devfn)) {
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case 0:
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dev->dev.platform_data = &db120_ath9k_data;
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break;
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}
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return 0;
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}
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static void __init db120_pci_init(u8 *eeprom)
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{
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memcpy(db120_ath9k_data.eeprom_data, eeprom,
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sizeof(db120_ath9k_data.eeprom_data));
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ath79_pci_set_plat_dev_init(db120_pci_plat_dev_init);
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ath79_register_pci();
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}
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#else
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static inline void db120_pci_init(void) {}
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#endif /* CONFIG_PCI */
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static void __init db120_setup(void)
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{
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u8 *art = (u8 *) KSEG1ADDR(0x1fff0000);
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ath79_register_leds_gpio(-1, ARRAY_SIZE(db120_leds_gpio),
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db120_leds_gpio);
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ath79_register_gpio_keys_polled(-1, DB120_KEYS_POLL_INTERVAL,
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ARRAY_SIZE(db120_gpio_keys),
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db120_gpio_keys);
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ath79_register_spi(&db120_spi_data, db120_spi_info,
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ARRAY_SIZE(db120_spi_info));
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ath79_register_usb();
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ath79_register_wmac(art + DB120_WMAC_CALDATA_OFFSET);
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db120_pci_init(art + DB120_PCIE_CALDATA_OFFSET);
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}
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MIPS_MACHINE(ATH79_MACH_DB120, "DB120", "Atheros DB120 reference board",
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db120_setup);
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