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6262db7c08
There is an ordering issue with spin_unlock_wait() on powerpc, because
the spin_lock primitive is an ACQUIRE and an ACQUIRE is only ordering
the load part of the operation with memory operations following it.
Therefore the following event sequence can happen:
CPU 1 CPU 2 CPU 3
================== ==================== ==============
spin_unlock(&lock);
spin_lock(&lock):
r1 = *lock; // r1 == 0;
o = object; o = READ_ONCE(object); // reordered here
object = NULL;
smp_mb();
spin_unlock_wait(&lock);
*lock = 1;
smp_mb();
o->dead = true; < o = READ_ONCE(object); > // reordered upwards
if (o) // true
BUG_ON(o->dead); // true!!
To fix this, we add a "nop" ll/sc loop in arch_spin_unlock_wait() on
ppc, the "nop" ll/sc loop reads the lock
value and writes it back atomically, in this way it will synchronize the
view of the lock on CPU1 with that on CPU2. Therefore in the scenario
above, either CPU2 will fail to get the lock at first or CPU1 will see
the lock acquired by CPU2, both cases will eliminate this bug. This is a
similar idea as what Will Deacon did for ARM64 in:
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| .. | ||
| alloc.c | ||
| checksum_32.S | ||
| checksum_64.S | ||
| checksum_wrappers.c | ||
| code-patching.c | ||
| copy_32.S | ||
| copypage_64.S | ||
| copypage_power7.S | ||
| copyuser_64.S | ||
| copyuser_power7.S | ||
| crtsavres.S | ||
| div64.S | ||
| feature-fixups-test.S | ||
| feature-fixups.c | ||
| hweight_64.S | ||
| ldstfp.S | ||
| locks.c | ||
| Makefile | ||
| mem_64.S | ||
| memcmp_64.S | ||
| memcpy_64.S | ||
| memcpy_power7.S | ||
| ppc_ksyms.c | ||
| rheap.c | ||
| sstep.c | ||
| string_64.S | ||
| string.S | ||
| usercopy_64.c | ||
| vmx-helper.c | ||
| xor_vmx.c | ||