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7ba64d82b3
The macro used gxbb_ prefix for clock definitions. In order to share the macro between gxbb and meson8b, the prefix must be moved to gxbb.c. Signed-off-by: Alexander Müller <serveralex@gmail.com> Signed-off-by: Michael Turquette <mturquette@baylibre.com> Link: lkml.kernel.org/r/1472319654-59048-6-git-send-email-serveralex@gmail.com
121 lines
3.0 KiB
C
121 lines
3.0 KiB
C
/*
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* Copyright (c) 2015 Endless Mobile, Inc.
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* Author: Carlo Caione <carlo@endlessm.com>
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License along with
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* this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#ifndef __CLKC_H
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#define __CLKC_H
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#define PMASK(width) GENMASK(width - 1, 0)
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#define SETPMASK(width, shift) GENMASK(shift + width - 1, shift)
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#define CLRPMASK(width, shift) (~SETPMASK(width, shift))
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#define PARM_GET(width, shift, reg) \
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(((reg) & SETPMASK(width, shift)) >> (shift))
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#define PARM_SET(width, shift, reg, val) \
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(((reg) & CLRPMASK(width, shift)) | (val << (shift)))
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#define MESON_PARM_APPLICABLE(p) (!!((p)->width))
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struct parm {
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u16 reg_off;
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u8 shift;
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u8 width;
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};
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struct pll_rate_table {
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unsigned long rate;
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u16 m;
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u16 n;
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u16 od;
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u16 od2;
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u16 frac;
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};
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#define PLL_RATE(_r, _m, _n, _od) \
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{ \
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.rate = (_r), \
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.m = (_m), \
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.n = (_n), \
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.od = (_od), \
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} \
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#define PLL_FRAC_RATE(_r, _m, _n, _od, _od2, _frac) \
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{ \
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.rate = (_r), \
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.m = (_m), \
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.n = (_n), \
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.od = (_od), \
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.od2 = (_od2), \
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.frac = (_frac), \
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} \
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struct meson_clk_pll {
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struct clk_hw hw;
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void __iomem *base;
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struct parm m;
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struct parm n;
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struct parm frac;
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struct parm od;
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struct parm od2;
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const struct pll_rate_table *rate_table;
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unsigned int rate_count;
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spinlock_t *lock;
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};
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#define to_meson_clk_pll(_hw) container_of(_hw, struct meson_clk_pll, hw)
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struct meson_clk_cpu {
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struct clk_hw hw;
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void __iomem *base;
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u16 reg_off;
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struct notifier_block clk_nb;
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const struct clk_div_table *div_table;
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};
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int meson_clk_cpu_notifier_cb(struct notifier_block *nb, unsigned long event,
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void *data);
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struct meson_clk_mpll {
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struct clk_hw hw;
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void __iomem *base;
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struct parm sdm;
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struct parm n2;
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/* FIXME ssen gate control? */
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spinlock_t *lock;
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};
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#define MESON_GATE(_name, _reg, _bit) \
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struct clk_gate _name = { \
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.reg = (void __iomem *) _reg, \
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.bit_idx = (_bit), \
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.lock = &clk_lock, \
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.hw.init = &(struct clk_init_data) { \
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.name = #_name, \
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.ops = &clk_gate_ops, \
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.parent_names = (const char *[]){ "clk81" }, \
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.num_parents = 1, \
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.flags = (CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED), \
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}, \
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};
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/* clk_ops */
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extern const struct clk_ops meson_clk_pll_ro_ops;
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extern const struct clk_ops meson_clk_pll_ops;
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extern const struct clk_ops meson_clk_cpu_ops;
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extern const struct clk_ops meson_clk_mpll_ro_ops;
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#endif /* __CLKC_H */
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