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https://github.com/edk2-porting/linux-next.git
synced 2024-12-25 21:54:06 +08:00
e443ed3560
It seems there is a thinko in the TLB invalidation code that makes the tlbie in the loop executed just once. The intended check was probably 'gt', not 'lt'. Signed-off-by: Anton Vorontsov <avorontsov@ru.mvista.com> Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
351 lines
6.6 KiB
ArmAsm
351 lines
6.6 KiB
ArmAsm
#include <linux/threads.h>
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#include <asm/processor.h>
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#include <asm/page.h>
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#include <asm/cputable.h>
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#include <asm/thread_info.h>
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#include <asm/ppc_asm.h>
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#include <asm/asm-offsets.h>
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#include <asm/mmu.h>
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/*
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* Structure for storing CPU registers on the save area.
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*/
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#define SL_SP 0
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#define SL_PC 4
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#define SL_MSR 8
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#define SL_SDR1 0xc
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#define SL_SPRG0 0x10 /* 4 sprg's */
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#define SL_DBAT0 0x20
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#define SL_IBAT0 0x28
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#define SL_DBAT1 0x30
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#define SL_IBAT1 0x38
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#define SL_DBAT2 0x40
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#define SL_IBAT2 0x48
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#define SL_DBAT3 0x50
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#define SL_IBAT3 0x58
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#define SL_TB 0x60
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#define SL_R2 0x68
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#define SL_CR 0x6c
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#define SL_LR 0x70
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#define SL_R12 0x74 /* r12 to r31 */
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#define SL_SIZE (SL_R12 + 80)
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.section .data
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.align 5
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_GLOBAL(swsusp_save_area)
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.space SL_SIZE
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.section .text
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.align 5
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_GLOBAL(swsusp_arch_suspend)
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lis r11,swsusp_save_area@h
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ori r11,r11,swsusp_save_area@l
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mflr r0
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stw r0,SL_LR(r11)
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mfcr r0
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stw r0,SL_CR(r11)
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stw r1,SL_SP(r11)
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stw r2,SL_R2(r11)
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stmw r12,SL_R12(r11)
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/* Save MSR & SDR1 */
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mfmsr r4
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stw r4,SL_MSR(r11)
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mfsdr1 r4
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stw r4,SL_SDR1(r11)
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/* Get a stable timebase and save it */
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1: mftbu r4
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stw r4,SL_TB(r11)
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mftb r5
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stw r5,SL_TB+4(r11)
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mftbu r3
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cmpw r3,r4
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bne 1b
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/* Save SPRGs */
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mfsprg r4,0
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stw r4,SL_SPRG0(r11)
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mfsprg r4,1
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stw r4,SL_SPRG0+4(r11)
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mfsprg r4,2
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stw r4,SL_SPRG0+8(r11)
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mfsprg r4,3
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stw r4,SL_SPRG0+12(r11)
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/* Save BATs */
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mfdbatu r4,0
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stw r4,SL_DBAT0(r11)
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mfdbatl r4,0
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stw r4,SL_DBAT0+4(r11)
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mfdbatu r4,1
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stw r4,SL_DBAT1(r11)
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mfdbatl r4,1
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stw r4,SL_DBAT1+4(r11)
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mfdbatu r4,2
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stw r4,SL_DBAT2(r11)
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mfdbatl r4,2
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stw r4,SL_DBAT2+4(r11)
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mfdbatu r4,3
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stw r4,SL_DBAT3(r11)
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mfdbatl r4,3
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stw r4,SL_DBAT3+4(r11)
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mfibatu r4,0
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stw r4,SL_IBAT0(r11)
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mfibatl r4,0
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stw r4,SL_IBAT0+4(r11)
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mfibatu r4,1
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stw r4,SL_IBAT1(r11)
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mfibatl r4,1
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stw r4,SL_IBAT1+4(r11)
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mfibatu r4,2
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stw r4,SL_IBAT2(r11)
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mfibatl r4,2
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stw r4,SL_IBAT2+4(r11)
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mfibatu r4,3
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stw r4,SL_IBAT3(r11)
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mfibatl r4,3
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stw r4,SL_IBAT3+4(r11)
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#if 0
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/* Backup various CPU config stuffs */
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bl __save_cpu_setup
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#endif
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/* Call the low level suspend stuff (we should probably have made
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* a stackframe...
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*/
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bl swsusp_save
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/* Restore LR from the save area */
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lis r11,swsusp_save_area@h
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ori r11,r11,swsusp_save_area@l
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lwz r0,SL_LR(r11)
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mtlr r0
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blr
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/* Resume code */
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_GLOBAL(swsusp_arch_resume)
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#ifdef CONFIG_ALTIVEC
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/* Stop pending alitvec streams and memory accesses */
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BEGIN_FTR_SECTION
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DSSALL
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END_FTR_SECTION_IFSET(CPU_FTR_ALTIVEC)
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#endif
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sync
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/* Disable MSR:DR to make sure we don't take a TLB or
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* hash miss during the copy, as our hash table will
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* for a while be unuseable. For .text, we assume we are
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* covered by a BAT. This works only for non-G5 at this
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* point. G5 will need a better approach, possibly using
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* a small temporary hash table filled with large mappings,
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* disabling the MMU completely isn't a good option for
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* performance reasons.
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* (Note that 750's may have the same performance issue as
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* the G5 in this case, we should investigate using moving
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* BATs for these CPUs)
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*/
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mfmsr r0
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sync
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rlwinm r0,r0,0,28,26 /* clear MSR_DR */
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mtmsr r0
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sync
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isync
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/* Load ptr the list of pages to copy in r3 */
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lis r11,(restore_pblist - KERNELBASE)@h
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ori r11,r11,restore_pblist@l
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lwz r10,0(r11)
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/* Copy the pages. This is a very basic implementation, to
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* be replaced by something more cache efficient */
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1:
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tophys(r3,r10)
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li r0,256
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mtctr r0
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lwz r11,pbe_address(r3) /* source */
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tophys(r5,r11)
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lwz r10,pbe_orig_address(r3) /* destination */
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tophys(r6,r10)
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2:
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lwz r8,0(r5)
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lwz r9,4(r5)
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lwz r10,8(r5)
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lwz r11,12(r5)
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addi r5,r5,16
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stw r8,0(r6)
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stw r9,4(r6)
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stw r10,8(r6)
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stw r11,12(r6)
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addi r6,r6,16
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bdnz 2b
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lwz r10,pbe_next(r3)
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cmpwi 0,r10,0
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bne 1b
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/* Do a very simple cache flush/inval of the L1 to ensure
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* coherency of the icache
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*/
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lis r3,0x0002
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mtctr r3
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li r3, 0
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1:
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lwz r0,0(r3)
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addi r3,r3,0x0020
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bdnz 1b
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isync
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sync
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/* Now flush those cache lines */
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lis r3,0x0002
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mtctr r3
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li r3, 0
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1:
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dcbf 0,r3
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addi r3,r3,0x0020
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bdnz 1b
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sync
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/* Ok, we are now running with the kernel data of the old
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* kernel fully restored. We can get to the save area
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* easily now. As for the rest of the code, it assumes the
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* loader kernel and the booted one are exactly identical
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*/
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lis r11,swsusp_save_area@h
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ori r11,r11,swsusp_save_area@l
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tophys(r11,r11)
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#if 0
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/* Restore various CPU config stuffs */
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bl __restore_cpu_setup
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#endif
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/* Restore the BATs, and SDR1. Then we can turn on the MMU.
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* This is a bit hairy as we are running out of those BATs,
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* but first, our code is probably in the icache, and we are
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* writing the same value to the BAT, so that should be fine,
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* though a better solution will have to be found long-term
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*/
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lwz r4,SL_SDR1(r11)
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mtsdr1 r4
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lwz r4,SL_SPRG0(r11)
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mtsprg 0,r4
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lwz r4,SL_SPRG0+4(r11)
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mtsprg 1,r4
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lwz r4,SL_SPRG0+8(r11)
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mtsprg 2,r4
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lwz r4,SL_SPRG0+12(r11)
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mtsprg 3,r4
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#if 0
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lwz r4,SL_DBAT0(r11)
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mtdbatu 0,r4
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lwz r4,SL_DBAT0+4(r11)
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mtdbatl 0,r4
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lwz r4,SL_DBAT1(r11)
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mtdbatu 1,r4
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lwz r4,SL_DBAT1+4(r11)
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mtdbatl 1,r4
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lwz r4,SL_DBAT2(r11)
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mtdbatu 2,r4
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lwz r4,SL_DBAT2+4(r11)
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mtdbatl 2,r4
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lwz r4,SL_DBAT3(r11)
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mtdbatu 3,r4
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lwz r4,SL_DBAT3+4(r11)
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mtdbatl 3,r4
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lwz r4,SL_IBAT0(r11)
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mtibatu 0,r4
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lwz r4,SL_IBAT0+4(r11)
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mtibatl 0,r4
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lwz r4,SL_IBAT1(r11)
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mtibatu 1,r4
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lwz r4,SL_IBAT1+4(r11)
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mtibatl 1,r4
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lwz r4,SL_IBAT2(r11)
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mtibatu 2,r4
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lwz r4,SL_IBAT2+4(r11)
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mtibatl 2,r4
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lwz r4,SL_IBAT3(r11)
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mtibatu 3,r4
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lwz r4,SL_IBAT3+4(r11)
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mtibatl 3,r4
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#endif
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BEGIN_MMU_FTR_SECTION
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li r4,0
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mtspr SPRN_DBAT4U,r4
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mtspr SPRN_DBAT4L,r4
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mtspr SPRN_DBAT5U,r4
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mtspr SPRN_DBAT5L,r4
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mtspr SPRN_DBAT6U,r4
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mtspr SPRN_DBAT6L,r4
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mtspr SPRN_DBAT7U,r4
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mtspr SPRN_DBAT7L,r4
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mtspr SPRN_IBAT4U,r4
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mtspr SPRN_IBAT4L,r4
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mtspr SPRN_IBAT5U,r4
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mtspr SPRN_IBAT5L,r4
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mtspr SPRN_IBAT6U,r4
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mtspr SPRN_IBAT6L,r4
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mtspr SPRN_IBAT7U,r4
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mtspr SPRN_IBAT7L,r4
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END_MMU_FTR_SECTION_IFSET(MMU_FTR_USE_HIGH_BATS)
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/* Flush all TLBs */
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lis r4,0x1000
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1: addic. r4,r4,-0x1000
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tlbie r4
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bgt 1b
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sync
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/* restore the MSR and turn on the MMU */
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lwz r3,SL_MSR(r11)
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bl turn_on_mmu
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tovirt(r11,r11)
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/* Restore TB */
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li r3,0
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mttbl r3
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lwz r3,SL_TB(r11)
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lwz r4,SL_TB+4(r11)
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mttbu r3
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mttbl r4
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/* Kick decrementer */
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li r0,1
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mtdec r0
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/* Restore the callee-saved registers and return */
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lwz r0,SL_CR(r11)
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mtcr r0
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lwz r2,SL_R2(r11)
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lmw r12,SL_R12(r11)
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lwz r1,SL_SP(r11)
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lwz r0,SL_LR(r11)
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mtlr r0
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// XXX Note: we don't really need to call swsusp_resume
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li r3,0
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blr
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/* FIXME:This construct is actually not useful since we don't shut
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* down the instruction MMU, we could just flip back MSR-DR on.
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*/
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turn_on_mmu:
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mflr r4
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mtsrr0 r4
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mtsrr1 r3
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sync
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isync
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rfi
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