Alex Frid 2f924ac33f clk: tegra: Fix T210 PLLRE registration ... Switched Tegra210 PLLRE registration to common PLL ops instead of special PLLRE ops used on previous Tegra chips. The latter ops do not follow chip specific PLL frequency table, and do not apply chip specific rate calculation method. Removed unnecessary default rate setting that duplicates h/w reset state, and is overwritten by clock initialization, anyway. Signed-off-by: Alex Frid <afrid@nvidia.com> Reviewed-by: Peter De Schrijver <pdeschrijver@nvidia.com> Reviewed-by: Jon Mayo <jmayo@nvidia.com> Tested-by: Thierry Reding <treding@nvidia.com> Acked-by: Thierry Reding <treding@nvidia.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>		2017-08-23 16:00:23 -07:00
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clk-audio-sync.c	clk: tegra: Remove CLK_IS_ROOT	2016-03-02 17:47:19 -08:00
clk-bpmp.c	clk: tegra: Add BPMP clock driver	2017-02-03 12:36:36 -08:00
clk-dfll.c	PM / OPP: Update OPP users to put reference	2017-01-30 09:22:21 +01:00
clk-dfll.h	clk: tegra: dfll: Properly clean up on failure and removal	2016-04-28 12:41:54 +02:00
clk-divider.c	tegra/clk-divider: fix wrong do_div() usage	2015-11-16 12:37:55 -05:00
clk-emc.c	clk: Convert to using %pOF instead of full_name	2017-07-21 15:49:54 -07:00
clk-id.h	clk: tegra: Add missing Tegra210 clocks	2017-04-04 16:03:00 +02:00
clk-periph-fixed.c	clk: tegra: Add fixed factor peripheral clock type	2016-04-28 12:41:47 +02:00
clk-periph-gate.c	clk: tegra: Fix disable unused for clocks sharing enable bit	2017-03-20 14:13:52 +01:00
clk-periph.c	clk: tegra: Fix build warnings on Tegra20/Tegra30	2017-03-20 17:14:14 +01:00
clk-pll-out.c	clk: tegra: Properly include clk.h	2015-07-20 11:11:17 -07:00
clk-pll.c	clk: tegra: Fix T210 PLLRE registration	2017-08-23 16:00:23 -07:00
clk-super.c	clk: tegra: Add super clock mux/divider	2017-03-20 14:07:33 +01:00
clk-tegra20.c	treewide: Fix typos in printk	2016-04-28 10:52:28 +02:00
clk-tegra30.c	clk: tegra: Add CEC clock	2017-03-20 14:06:23 +01:00
clk-tegra114.c	clk: tegra: Add CEC clock	2017-03-20 14:06:23 +01:00
clk-tegra124-dfll-fcpu.c	clk: tegra: dfll: Use builtin_platform_driver to simplify the code	2016-11-10 14:08:46 -08:00
clk-tegra124.c	clk: tegra: Add CEC clock	2017-03-20 14:06:23 +01:00
clk-tegra210.c	clk: tegra: Re-factor T210 PLLX registration	2017-08-23 15:59:59 -07:00
clk-tegra-audio.c	clk: tegra: Define Tegra210 DMIC sync clocks	2017-03-20 14:06:33 +01:00
clk-tegra-fixed.c	clk: tegra: Remove trailing blank line	2016-04-28 12:41:45 +02:00
clk-tegra-periph.c	clk: tegra: Add TEGRA_PERIPH_ON_APB flag to I2C	2017-08-23 15:59:33 -07:00
clk-tegra-pmc.c	clk: tegra: Propagate clk_out_x rate to parent	2017-04-04 16:00:28 +02:00
clk-tegra-super-gen4.c	clk: tegra: Re-factor T210 PLLX registration	2017-08-23 15:59:59 -07:00
clk.c	clk: tegra: Implement reset control reset	2017-03-20 14:15:31 +01:00
clk.h	clk: tegra: Re-factor T210 PLLX registration	2017-08-23 15:59:59 -07:00
cvb.c	clk: tegra: dfll: improve function-level documentation	2016-11-01 17:38:50 -07:00
cvb.h	clk: tegra: dfll: Properly clean up on failure and removal	2016-04-28 12:41:54 +02:00
Kconfig	clk: tegra: Add BPMP clock driver	2017-02-03 12:36:36 -08:00
Makefile	clk: tegra: Add BPMP clock driver	2017-02-03 12:36:36 -08:00