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0a11a6ae94
Init order of CLK_OF_DECLARE'd drivers depends on compile order. Unfortunately, clk_of_init does not allow drivers to return errors, e.g. -EPROBE_DEFER if parent clocks have not been registered, yet. To avoid init order woes for MVEBU clock drivers, we take care of proper init order ourselves. This patch joins core-clk and gating-clk init to maintain proper init order. Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com> Signed-off-by: Jason Cooper <jason@lakedaemon.net>
209 lines
5.5 KiB
C
209 lines
5.5 KiB
C
/*
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* Marvell Armada XP SoC clocks
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*
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* Copyright (C) 2012 Marvell
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*
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* Gregory CLEMENT <gregory.clement@free-electrons.com>
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* Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
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* Andrew Lunn <andrew@lunn.ch>
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*
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* This file is licensed under the terms of the GNU General Public
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* License version 2. This program is licensed "as is" without any
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* warranty of any kind, whether express or implied.
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*/
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#include <linux/kernel.h>
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#include <linux/clk-provider.h>
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#include <linux/io.h>
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#include <linux/of.h>
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#include "common.h"
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/*
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* Core Clocks
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*
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* Armada XP Sample At Reset is a 64 bit bitfiled split in two
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* register of 32 bits
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*/
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#define SARL 0 /* Low part [0:31] */
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#define SARL_AXP_PCLK_FREQ_OPT 21
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#define SARL_AXP_PCLK_FREQ_OPT_MASK 0x7
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#define SARL_AXP_FAB_FREQ_OPT 24
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#define SARL_AXP_FAB_FREQ_OPT_MASK 0xF
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#define SARH 4 /* High part [32:63] */
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#define SARH_AXP_PCLK_FREQ_OPT (52-32)
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#define SARH_AXP_PCLK_FREQ_OPT_MASK 0x1
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#define SARH_AXP_PCLK_FREQ_OPT_SHIFT 3
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#define SARH_AXP_FAB_FREQ_OPT (51-32)
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#define SARH_AXP_FAB_FREQ_OPT_MASK 0x1
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#define SARH_AXP_FAB_FREQ_OPT_SHIFT 4
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enum { AXP_CPU_TO_NBCLK, AXP_CPU_TO_HCLK, AXP_CPU_TO_DRAMCLK };
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static const struct coreclk_ratio axp_coreclk_ratios[] __initconst = {
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{ .id = AXP_CPU_TO_NBCLK, .name = "nbclk" },
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{ .id = AXP_CPU_TO_HCLK, .name = "hclk" },
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{ .id = AXP_CPU_TO_DRAMCLK, .name = "dramclk" },
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};
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/* Armada XP TCLK frequency is fixed to 250MHz */
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static u32 __init axp_get_tclk_freq(void __iomem *sar)
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{
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return 250000000;
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}
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static const u32 axp_cpu_freqs[] __initconst = {
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1000000000,
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1066000000,
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1200000000,
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1333000000,
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1500000000,
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1666000000,
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1800000000,
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2000000000,
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667000000,
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0,
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800000000,
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1600000000,
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};
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static u32 __init axp_get_cpu_freq(void __iomem *sar)
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{
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u32 cpu_freq;
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u8 cpu_freq_select = 0;
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cpu_freq_select = ((readl(sar + SARL) >> SARL_AXP_PCLK_FREQ_OPT) &
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SARL_AXP_PCLK_FREQ_OPT_MASK);
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/*
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* The upper bit is not contiguous to the other ones and
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* located in the high part of the SAR registers
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*/
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cpu_freq_select |= (((readl(sar + SARH) >> SARH_AXP_PCLK_FREQ_OPT) &
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SARH_AXP_PCLK_FREQ_OPT_MASK) << SARH_AXP_PCLK_FREQ_OPT_SHIFT);
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if (cpu_freq_select >= ARRAY_SIZE(axp_cpu_freqs)) {
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pr_err("CPU freq select unsupported: %d\n", cpu_freq_select);
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cpu_freq = 0;
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} else
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cpu_freq = axp_cpu_freqs[cpu_freq_select];
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return cpu_freq;
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}
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static const int axp_nbclk_ratios[32][2] __initconst = {
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{0, 1}, {1, 2}, {2, 2}, {2, 2},
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{1, 2}, {1, 2}, {1, 1}, {2, 3},
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{0, 1}, {1, 2}, {2, 4}, {0, 1},
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{1, 2}, {0, 1}, {0, 1}, {2, 2},
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{0, 1}, {0, 1}, {0, 1}, {1, 1},
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{2, 3}, {0, 1}, {0, 1}, {0, 1},
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{0, 1}, {0, 1}, {0, 1}, {1, 1},
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{0, 1}, {0, 1}, {0, 1}, {0, 1},
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};
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static const int axp_hclk_ratios[32][2] __initconst = {
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{0, 1}, {1, 2}, {2, 6}, {2, 3},
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{1, 3}, {1, 4}, {1, 2}, {2, 6},
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{0, 1}, {1, 6}, {2, 10}, {0, 1},
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{1, 4}, {0, 1}, {0, 1}, {2, 5},
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{0, 1}, {0, 1}, {0, 1}, {1, 2},
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{2, 6}, {0, 1}, {0, 1}, {0, 1},
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{0, 1}, {0, 1}, {0, 1}, {1, 1},
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{0, 1}, {0, 1}, {0, 1}, {0, 1},
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};
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static const int axp_dramclk_ratios[32][2] __initconst = {
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{0, 1}, {1, 2}, {2, 3}, {2, 3},
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{1, 3}, {1, 2}, {1, 2}, {2, 6},
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{0, 1}, {1, 3}, {2, 5}, {0, 1},
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{1, 4}, {0, 1}, {0, 1}, {2, 5},
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{0, 1}, {0, 1}, {0, 1}, {1, 1},
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{2, 3}, {0, 1}, {0, 1}, {0, 1},
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{0, 1}, {0, 1}, {0, 1}, {1, 1},
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{0, 1}, {0, 1}, {0, 1}, {0, 1},
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};
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static void __init axp_get_clk_ratio(
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void __iomem *sar, int id, int *mult, int *div)
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{
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u32 opt = ((readl(sar + SARL) >> SARL_AXP_FAB_FREQ_OPT) &
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SARL_AXP_FAB_FREQ_OPT_MASK);
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/*
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* The upper bit is not contiguous to the other ones and
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* located in the high part of the SAR registers
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*/
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opt |= (((readl(sar + SARH) >> SARH_AXP_FAB_FREQ_OPT) &
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SARH_AXP_FAB_FREQ_OPT_MASK) << SARH_AXP_FAB_FREQ_OPT_SHIFT);
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switch (id) {
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case AXP_CPU_TO_NBCLK:
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*mult = axp_nbclk_ratios[opt][0];
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*div = axp_nbclk_ratios[opt][1];
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break;
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case AXP_CPU_TO_HCLK:
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*mult = axp_hclk_ratios[opt][0];
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*div = axp_hclk_ratios[opt][1];
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break;
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case AXP_CPU_TO_DRAMCLK:
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*mult = axp_dramclk_ratios[opt][0];
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*div = axp_dramclk_ratios[opt][1];
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break;
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}
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}
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static const struct coreclk_soc_desc axp_coreclks = {
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.get_tclk_freq = axp_get_tclk_freq,
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.get_cpu_freq = axp_get_cpu_freq,
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.get_clk_ratio = axp_get_clk_ratio,
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.ratios = axp_coreclk_ratios,
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.num_ratios = ARRAY_SIZE(axp_coreclk_ratios),
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};
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/*
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* Clock Gating Control
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*/
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static const struct clk_gating_soc_desc axp_gating_desc[] __initconst = {
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{ "audio", NULL, 0, 0 },
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{ "ge3", NULL, 1, 0 },
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{ "ge2", NULL, 2, 0 },
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{ "ge1", NULL, 3, 0 },
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{ "ge0", NULL, 4, 0 },
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{ "pex00", NULL, 5, 0 },
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{ "pex01", NULL, 6, 0 },
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{ "pex02", NULL, 7, 0 },
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{ "pex03", NULL, 8, 0 },
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{ "pex10", NULL, 9, 0 },
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{ "pex11", NULL, 10, 0 },
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{ "pex12", NULL, 11, 0 },
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{ "pex13", NULL, 12, 0 },
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{ "bp", NULL, 13, 0 },
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{ "sata0lnk", NULL, 14, 0 },
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{ "sata0", "sata0lnk", 15, 0 },
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{ "lcd", NULL, 16, 0 },
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{ "sdio", NULL, 17, 0 },
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{ "usb0", NULL, 18, 0 },
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{ "usb1", NULL, 19, 0 },
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{ "usb2", NULL, 20, 0 },
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{ "xor0", NULL, 22, 0 },
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{ "crypto", NULL, 23, 0 },
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{ "tdm", NULL, 25, 0 },
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{ "pex20", NULL, 26, 0 },
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{ "pex30", NULL, 27, 0 },
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{ "xor1", NULL, 28, 0 },
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{ "sata1lnk", NULL, 29, 0 },
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{ "sata1", "sata1lnk", 30, 0 },
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{ }
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};
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static void __init axp_clk_init(struct device_node *np)
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{
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struct device_node *cgnp =
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of_find_compatible_node(NULL, NULL, "marvell,armada-xp-gating-clock");
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mvebu_coreclk_setup(np, &axp_coreclks);
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if (cgnp)
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mvebu_clk_gating_setup(cgnp, axp_gating_desc);
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}
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CLK_OF_DECLARE(axp_clk, "marvell,armada-xp-core-clock", axp_clk_init);
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