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b0161caa72
When refactoring and breaking out the includes for the machine-specific GPIO configuration, two files were created in <linux/platform_data/gpio-samsung-s3c[24|64]xx.h>, but as that namespace shall be used for defining data exchanged between machines and drivers, using it for these broad macros and config settings is wrong. Move the headers back into the machine-local <mach/gpio-samsung.h> file and think about the next step. Reported-by: Arnd Bergmann <arnd@arndb.de> Cc: Tomasz Figa <tomasz.figa@gmail.com> Cc: Sylwester Nawrocki <sylvester.nawrocki@gmail.com> Cc: Ben Dooks <ben-linux@fluff.org> Cc: Kukjin Kim <kgene.kim@samsung.com> Cc: linux-samsung-soc@vger.kernel.org Acked-by: Mark Brown <broonie@linaro.org> Acked-by: Arnd Bergmann <arnd@arndb.de> Acked-by: Heiko Stuebner <heiko@sntech.de> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
45 lines
1.3 KiB
C
45 lines
1.3 KiB
C
/* linux/arch/arm/mach-s3c64xx/setup-ide.c
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*
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* Copyright (c) 2010 Samsung Electronics Co., Ltd.
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* http://www.samsung.com/
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*
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* S3C64XX setup information for IDE
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#include <linux/kernel.h>
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#include <linux/gpio.h>
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#include <linux/io.h>
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#include <mach/map.h>
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#include <mach/regs-clock.h>
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#include <plat/gpio-cfg.h>
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#include <mach/gpio-samsung.h>
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#include <linux/platform_data/ata-samsung_cf.h>
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void s3c64xx_ide_setup_gpio(void)
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{
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u32 reg;
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reg = readl(S3C_MEM_SYS_CFG) & (~0x3f);
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/* Independent CF interface, CF chip select configuration */
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writel(reg | MEM_SYS_CFG_INDEP_CF |
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MEM_SYS_CFG_EBI_FIX_PRI_CFCON, S3C_MEM_SYS_CFG);
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s3c_gpio_cfgpin(S3C64XX_GPB(4), S3C_GPIO_SFN(4));
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/* Set XhiDATA[15:0] pins as CF Data[15:0] */
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s3c_gpio_cfgpin_range(S3C64XX_GPK(0), 16, S3C_GPIO_SFN(5));
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/* Set XhiADDR[2:0] pins as CF ADDR[2:0] */
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s3c_gpio_cfgpin_range(S3C64XX_GPL(0), 3, S3C_GPIO_SFN(6));
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/* Set Xhi ctrl pins as CF ctrl pins(IORDY, IOWR, IORD, CE[0:1]) */
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s3c_gpio_cfgpin(S3C64XX_GPM(5), S3C_GPIO_SFN(1));
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s3c_gpio_cfgpin_range(S3C64XX_GPM(0), 5, S3C_GPIO_SFN(6));
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}
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