mirror of
https://github.com/edk2-porting/linux-next.git
synced 2025-01-06 12:44:14 +08:00
6218590bcb
All architectures:
Move `make kvmconfig` stubs from x86; use 64 bits for debugfs stats.
ARM:
Important fixes for not using an in-kernel irqchip; handle SError
exceptions and present them to guests if appropriate; proxying of GICV
access at EL2 if guest mappings are unsafe; GICv3 on AArch32 on ARMv8;
preparations for GICv3 save/restore, including ABI docs; cleanups and
a bit of optimizations.
MIPS:
A couple of fixes in preparation for supporting MIPS EVA host kernels;
MIPS SMP host & TLB invalidation fixes.
PPC:
Fix the bug which caused guests to falsely report lockups; other minor
fixes; a small optimization.
s390:
Lazy enablement of runtime instrumentation; up to 255 CPUs for nested
guests; rework of machine check deliver; cleanups and fixes.
x86:
IOMMU part of AMD's AVIC for vmexit-less interrupt delivery; Hyper-V
TSC page; per-vcpu tsc_offset in debugfs; accelerated INS/OUTS in
nVMX; cleanups and fixes.
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Merge tag 'kvm-4.9-1' of git://git.kernel.org/pub/scm/virt/kvm/kvm
Pull KVM updates from Radim Krčmář:
"All architectures:
- move `make kvmconfig` stubs from x86
- use 64 bits for debugfs stats
ARM:
- Important fixes for not using an in-kernel irqchip
- handle SError exceptions and present them to guests if appropriate
- proxying of GICV access at EL2 if guest mappings are unsafe
- GICv3 on AArch32 on ARMv8
- preparations for GICv3 save/restore, including ABI docs
- cleanups and a bit of optimizations
MIPS:
- A couple of fixes in preparation for supporting MIPS EVA host
kernels
- MIPS SMP host & TLB invalidation fixes
PPC:
- Fix the bug which caused guests to falsely report lockups
- other minor fixes
- a small optimization
s390:
- Lazy enablement of runtime instrumentation
- up to 255 CPUs for nested guests
- rework of machine check deliver
- cleanups and fixes
x86:
- IOMMU part of AMD's AVIC for vmexit-less interrupt delivery
- Hyper-V TSC page
- per-vcpu tsc_offset in debugfs
- accelerated INS/OUTS in nVMX
- cleanups and fixes"
* tag 'kvm-4.9-1' of git://git.kernel.org/pub/scm/virt/kvm/kvm: (140 commits)
KVM: MIPS: Drop dubious EntryHi optimisation
KVM: MIPS: Invalidate TLB by regenerating ASIDs
KVM: MIPS: Split kernel/user ASID regeneration
KVM: MIPS: Drop other CPU ASIDs on guest MMU changes
KVM: arm/arm64: vgic: Don't flush/sync without a working vgic
KVM: arm64: Require in-kernel irqchip for PMU support
KVM: PPC: Book3s PR: Allow access to unprivileged MMCR2 register
KVM: PPC: Book3S PR: Support 64kB page size on POWER8E and POWER8NVL
KVM: PPC: Book3S: Remove duplicate setting of the B field in tlbie
KVM: PPC: BookE: Fix a sanity check
KVM: PPC: Book3S HV: Take out virtual core piggybacking code
KVM: PPC: Book3S: Treat VTB as a per-subcore register, not per-thread
ARM: gic-v3: Work around definition of gic_write_bpr1
KVM: nVMX: Fix the NMI IDT-vectoring handling
KVM: VMX: Enable MSR-BASED TPR shadow even if APICv is inactive
KVM: nVMX: Fix reload apic access page warning
kvmconfig: add virtio-gpu to config fragment
config: move x86 kvm_guest.config to a common location
arm64: KVM: Remove duplicating init code for setting VMID
ARM: KVM: Support vgic-v3
...
256 lines
7.0 KiB
C
256 lines
7.0 KiB
C
/*
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* arch/arm/include/asm/arch_gicv3.h
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*
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* Copyright (C) 2015 ARM Ltd.
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*
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* This program is free software: you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#ifndef __ASM_ARCH_GICV3_H
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#define __ASM_ARCH_GICV3_H
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#ifndef __ASSEMBLY__
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#include <linux/io.h>
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#include <asm/barrier.h>
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#include <asm/cp15.h>
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#define ICC_EOIR1 __ACCESS_CP15(c12, 0, c12, 1)
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#define ICC_DIR __ACCESS_CP15(c12, 0, c11, 1)
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#define ICC_IAR1 __ACCESS_CP15(c12, 0, c12, 0)
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#define ICC_SGI1R __ACCESS_CP15_64(0, c12)
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#define ICC_PMR __ACCESS_CP15(c4, 0, c6, 0)
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#define ICC_CTLR __ACCESS_CP15(c12, 0, c12, 4)
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#define ICC_SRE __ACCESS_CP15(c12, 0, c12, 5)
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#define ICC_IGRPEN1 __ACCESS_CP15(c12, 0, c12, 7)
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#define ICC_BPR1 __ACCESS_CP15(c12, 0, c12, 3)
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#define ICC_HSRE __ACCESS_CP15(c12, 4, c9, 5)
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#define ICH_VSEIR __ACCESS_CP15(c12, 4, c9, 4)
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#define ICH_HCR __ACCESS_CP15(c12, 4, c11, 0)
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#define ICH_VTR __ACCESS_CP15(c12, 4, c11, 1)
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#define ICH_MISR __ACCESS_CP15(c12, 4, c11, 2)
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#define ICH_EISR __ACCESS_CP15(c12, 4, c11, 3)
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#define ICH_ELSR __ACCESS_CP15(c12, 4, c11, 5)
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#define ICH_VMCR __ACCESS_CP15(c12, 4, c11, 7)
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#define __LR0(x) __ACCESS_CP15(c12, 4, c12, x)
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#define __LR8(x) __ACCESS_CP15(c12, 4, c13, x)
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#define ICH_LR0 __LR0(0)
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#define ICH_LR1 __LR0(1)
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#define ICH_LR2 __LR0(2)
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#define ICH_LR3 __LR0(3)
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#define ICH_LR4 __LR0(4)
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#define ICH_LR5 __LR0(5)
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#define ICH_LR6 __LR0(6)
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#define ICH_LR7 __LR0(7)
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#define ICH_LR8 __LR8(0)
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#define ICH_LR9 __LR8(1)
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#define ICH_LR10 __LR8(2)
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#define ICH_LR11 __LR8(3)
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#define ICH_LR12 __LR8(4)
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#define ICH_LR13 __LR8(5)
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#define ICH_LR14 __LR8(6)
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#define ICH_LR15 __LR8(7)
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/* LR top half */
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#define __LRC0(x) __ACCESS_CP15(c12, 4, c14, x)
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#define __LRC8(x) __ACCESS_CP15(c12, 4, c15, x)
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#define ICH_LRC0 __LRC0(0)
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#define ICH_LRC1 __LRC0(1)
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#define ICH_LRC2 __LRC0(2)
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#define ICH_LRC3 __LRC0(3)
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#define ICH_LRC4 __LRC0(4)
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#define ICH_LRC5 __LRC0(5)
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#define ICH_LRC6 __LRC0(6)
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#define ICH_LRC7 __LRC0(7)
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#define ICH_LRC8 __LRC8(0)
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#define ICH_LRC9 __LRC8(1)
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#define ICH_LRC10 __LRC8(2)
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#define ICH_LRC11 __LRC8(3)
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#define ICH_LRC12 __LRC8(4)
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#define ICH_LRC13 __LRC8(5)
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#define ICH_LRC14 __LRC8(6)
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#define ICH_LRC15 __LRC8(7)
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#define __AP0Rx(x) __ACCESS_CP15(c12, 4, c8, x)
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#define ICH_AP0R0 __AP0Rx(0)
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#define ICH_AP0R1 __AP0Rx(1)
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#define ICH_AP0R2 __AP0Rx(2)
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#define ICH_AP0R3 __AP0Rx(3)
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#define __AP1Rx(x) __ACCESS_CP15(c12, 4, c9, x)
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#define ICH_AP1R0 __AP1Rx(0)
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#define ICH_AP1R1 __AP1Rx(1)
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#define ICH_AP1R2 __AP1Rx(2)
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#define ICH_AP1R3 __AP1Rx(3)
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/* A32-to-A64 mappings used by VGIC save/restore */
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#define CPUIF_MAP(a32, a64) \
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static inline void write_ ## a64(u32 val) \
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{ \
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write_sysreg(val, a32); \
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} \
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static inline u32 read_ ## a64(void) \
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{ \
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return read_sysreg(a32); \
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} \
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#define CPUIF_MAP_LO_HI(a32lo, a32hi, a64) \
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static inline void write_ ## a64(u64 val) \
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{ \
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write_sysreg(lower_32_bits(val), a32lo);\
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write_sysreg(upper_32_bits(val), a32hi);\
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} \
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static inline u64 read_ ## a64(void) \
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{ \
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u64 val = read_sysreg(a32lo); \
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\
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val |= (u64)read_sysreg(a32hi) << 32; \
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\
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return val; \
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}
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CPUIF_MAP(ICH_HCR, ICH_HCR_EL2)
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CPUIF_MAP(ICH_VTR, ICH_VTR_EL2)
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CPUIF_MAP(ICH_MISR, ICH_MISR_EL2)
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CPUIF_MAP(ICH_EISR, ICH_EISR_EL2)
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CPUIF_MAP(ICH_ELSR, ICH_ELSR_EL2)
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CPUIF_MAP(ICH_VMCR, ICH_VMCR_EL2)
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CPUIF_MAP(ICH_AP0R3, ICH_AP0R3_EL2)
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CPUIF_MAP(ICH_AP0R2, ICH_AP0R2_EL2)
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CPUIF_MAP(ICH_AP0R1, ICH_AP0R1_EL2)
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CPUIF_MAP(ICH_AP0R0, ICH_AP0R0_EL2)
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CPUIF_MAP(ICH_AP1R3, ICH_AP1R3_EL2)
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CPUIF_MAP(ICH_AP1R2, ICH_AP1R2_EL2)
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CPUIF_MAP(ICH_AP1R1, ICH_AP1R1_EL2)
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CPUIF_MAP(ICH_AP1R0, ICH_AP1R0_EL2)
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CPUIF_MAP(ICC_HSRE, ICC_SRE_EL2)
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CPUIF_MAP(ICC_SRE, ICC_SRE_EL1)
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CPUIF_MAP_LO_HI(ICH_LR15, ICH_LRC15, ICH_LR15_EL2)
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CPUIF_MAP_LO_HI(ICH_LR14, ICH_LRC14, ICH_LR14_EL2)
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CPUIF_MAP_LO_HI(ICH_LR13, ICH_LRC13, ICH_LR13_EL2)
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CPUIF_MAP_LO_HI(ICH_LR12, ICH_LRC12, ICH_LR12_EL2)
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CPUIF_MAP_LO_HI(ICH_LR11, ICH_LRC11, ICH_LR11_EL2)
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CPUIF_MAP_LO_HI(ICH_LR10, ICH_LRC10, ICH_LR10_EL2)
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CPUIF_MAP_LO_HI(ICH_LR9, ICH_LRC9, ICH_LR9_EL2)
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CPUIF_MAP_LO_HI(ICH_LR8, ICH_LRC8, ICH_LR8_EL2)
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CPUIF_MAP_LO_HI(ICH_LR7, ICH_LRC7, ICH_LR7_EL2)
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CPUIF_MAP_LO_HI(ICH_LR6, ICH_LRC6, ICH_LR6_EL2)
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CPUIF_MAP_LO_HI(ICH_LR5, ICH_LRC5, ICH_LR5_EL2)
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CPUIF_MAP_LO_HI(ICH_LR4, ICH_LRC4, ICH_LR4_EL2)
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CPUIF_MAP_LO_HI(ICH_LR3, ICH_LRC3, ICH_LR3_EL2)
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CPUIF_MAP_LO_HI(ICH_LR2, ICH_LRC2, ICH_LR2_EL2)
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CPUIF_MAP_LO_HI(ICH_LR1, ICH_LRC1, ICH_LR1_EL2)
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CPUIF_MAP_LO_HI(ICH_LR0, ICH_LRC0, ICH_LR0_EL2)
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#define read_gicreg(r) read_##r()
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#define write_gicreg(v, r) write_##r(v)
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/* Low-level accessors */
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static inline void gic_write_eoir(u32 irq)
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{
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write_sysreg(irq, ICC_EOIR1);
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isb();
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}
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static inline void gic_write_dir(u32 val)
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{
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write_sysreg(val, ICC_DIR);
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isb();
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}
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static inline u32 gic_read_iar(void)
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{
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u32 irqstat = read_sysreg(ICC_IAR1);
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dsb(sy);
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return irqstat;
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}
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static inline void gic_write_pmr(u32 val)
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{
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write_sysreg(val, ICC_PMR);
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}
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static inline void gic_write_ctlr(u32 val)
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{
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write_sysreg(val, ICC_CTLR);
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isb();
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}
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static inline void gic_write_grpen1(u32 val)
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{
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write_sysreg(val, ICC_IGRPEN1);
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isb();
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}
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static inline void gic_write_sgi1r(u64 val)
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{
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write_sysreg(val, ICC_SGI1R);
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}
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static inline u32 gic_read_sre(void)
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{
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return read_sysreg(ICC_SRE);
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}
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static inline void gic_write_sre(u32 val)
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{
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write_sysreg(val, ICC_SRE);
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isb();
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}
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static inline void gic_write_bpr1(u32 val)
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{
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write_sysreg(val, ICC_BPR1);
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}
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/*
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* Even in 32bit systems that use LPAE, there is no guarantee that the I/O
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* interface provides true 64bit atomic accesses, so using strd/ldrd doesn't
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* make much sense.
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* Moreover, 64bit I/O emulation is extremely difficult to implement on
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* AArch32, since the syndrome register doesn't provide any information for
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* them.
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* Consequently, the following IO helpers use 32bit accesses.
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*
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* There are only two registers that need 64bit accesses in this driver:
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* - GICD_IROUTERn, contain the affinity values associated to each interrupt.
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* The upper-word (aff3) will always be 0, so there is no need for a lock.
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* - GICR_TYPER is an ID register and doesn't need atomicity.
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*/
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static inline void gic_write_irouter(u64 val, volatile void __iomem *addr)
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{
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writel_relaxed((u32)val, addr);
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writel_relaxed((u32)(val >> 32), addr + 4);
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}
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static inline u64 gic_read_typer(const volatile void __iomem *addr)
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{
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u64 val;
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val = readl_relaxed(addr);
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val |= (u64)readl_relaxed(addr + 4) << 32;
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return val;
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}
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#endif /* !__ASSEMBLY__ */
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#endif /* !__ASM_ARCH_GICV3_H */
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