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e5674ad6ca
partial_fixup is used in noreorder block. Separating two consecutive loads can save one cycle on processors with GPR intrelock and can fix load-use on processors that need a load delay slot. Also do so for fwd_fixup. [Ralf: Only R2000/R3000 class processors are lacking the the load-user interlock and even some of those got it retrofitted. With R2000/R3000 being fairly uncommon these days the impact of this bug should be minor.] Signed-off-by: Tony Wu <tung7970@gmail.com> To: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/1768/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
181 lines
4.1 KiB
ArmAsm
181 lines
4.1 KiB
ArmAsm
/*
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* This file is subject to the terms and conditions of the GNU General Public
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* License. See the file "COPYING" in the main directory of this archive
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* for more details.
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*
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* Copyright (C) 1998, 1999, 2000 by Ralf Baechle
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* Copyright (C) 1999, 2000 Silicon Graphics, Inc.
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* Copyright (C) 2007 Maciej W. Rozycki
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*/
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#include <asm/asm.h>
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#include <asm/asm-offsets.h>
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#include <asm/regdef.h>
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#if LONGSIZE == 4
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#define LONG_S_L swl
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#define LONG_S_R swr
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#else
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#define LONG_S_L sdl
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#define LONG_S_R sdr
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#endif
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#define EX(insn,reg,addr,handler) \
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9: insn reg, addr; \
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.section __ex_table,"a"; \
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PTR 9b, handler; \
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.previous
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.macro f_fill64 dst, offset, val, fixup
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EX(LONG_S, \val, (\offset + 0 * LONGSIZE)(\dst), \fixup)
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EX(LONG_S, \val, (\offset + 1 * LONGSIZE)(\dst), \fixup)
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EX(LONG_S, \val, (\offset + 2 * LONGSIZE)(\dst), \fixup)
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EX(LONG_S, \val, (\offset + 3 * LONGSIZE)(\dst), \fixup)
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EX(LONG_S, \val, (\offset + 4 * LONGSIZE)(\dst), \fixup)
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EX(LONG_S, \val, (\offset + 5 * LONGSIZE)(\dst), \fixup)
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EX(LONG_S, \val, (\offset + 6 * LONGSIZE)(\dst), \fixup)
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EX(LONG_S, \val, (\offset + 7 * LONGSIZE)(\dst), \fixup)
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#if LONGSIZE == 4
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EX(LONG_S, \val, (\offset + 8 * LONGSIZE)(\dst), \fixup)
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EX(LONG_S, \val, (\offset + 9 * LONGSIZE)(\dst), \fixup)
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EX(LONG_S, \val, (\offset + 10 * LONGSIZE)(\dst), \fixup)
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EX(LONG_S, \val, (\offset + 11 * LONGSIZE)(\dst), \fixup)
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EX(LONG_S, \val, (\offset + 12 * LONGSIZE)(\dst), \fixup)
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EX(LONG_S, \val, (\offset + 13 * LONGSIZE)(\dst), \fixup)
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EX(LONG_S, \val, (\offset + 14 * LONGSIZE)(\dst), \fixup)
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EX(LONG_S, \val, (\offset + 15 * LONGSIZE)(\dst), \fixup)
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#endif
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.endm
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/*
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* memset(void *s, int c, size_t n)
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*
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* a0: start of area to clear
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* a1: char to fill with
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* a2: size of area to clear
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*/
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.set noreorder
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.align 5
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LEAF(memset)
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beqz a1, 1f
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move v0, a0 /* result */
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andi a1, 0xff /* spread fillword */
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LONG_SLL t1, a1, 8
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or a1, t1
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LONG_SLL t1, a1, 16
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#if LONGSIZE == 8
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or a1, t1
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LONG_SLL t1, a1, 32
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#endif
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or a1, t1
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1:
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FEXPORT(__bzero)
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sltiu t0, a2, LONGSIZE /* very small region? */
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bnez t0, .Lsmall_memset
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andi t0, a0, LONGMASK /* aligned? */
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#ifndef CONFIG_CPU_DADDI_WORKAROUNDS
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beqz t0, 1f
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PTR_SUBU t0, LONGSIZE /* alignment in bytes */
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#else
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.set noat
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li AT, LONGSIZE
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beqz t0, 1f
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PTR_SUBU t0, AT /* alignment in bytes */
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.set at
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#endif
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R10KCBARRIER(0(ra))
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#ifdef __MIPSEB__
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EX(LONG_S_L, a1, (a0), .Lfirst_fixup) /* make word/dword aligned */
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#endif
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#ifdef __MIPSEL__
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EX(LONG_S_R, a1, (a0), .Lfirst_fixup) /* make word/dword aligned */
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#endif
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PTR_SUBU a0, t0 /* long align ptr */
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PTR_ADDU a2, t0 /* correct size */
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1: ori t1, a2, 0x3f /* # of full blocks */
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xori t1, 0x3f
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beqz t1, .Lmemset_partial /* no block to fill */
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andi t0, a2, 0x40-LONGSIZE
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PTR_ADDU t1, a0 /* end address */
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.set reorder
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1: PTR_ADDIU a0, 64
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R10KCBARRIER(0(ra))
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f_fill64 a0, -64, a1, .Lfwd_fixup
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bne t1, a0, 1b
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.set noreorder
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.Lmemset_partial:
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R10KCBARRIER(0(ra))
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PTR_LA t1, 2f /* where to start */
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#if LONGSIZE == 4
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PTR_SUBU t1, t0
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#else
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.set noat
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LONG_SRL AT, t0, 1
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PTR_SUBU t1, AT
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.set at
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#endif
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jr t1
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PTR_ADDU a0, t0 /* dest ptr */
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.set push
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.set noreorder
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.set nomacro
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f_fill64 a0, -64, a1, .Lpartial_fixup /* ... but first do longs ... */
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2: .set pop
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andi a2, LONGMASK /* At most one long to go */
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beqz a2, 1f
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PTR_ADDU a0, a2 /* What's left */
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R10KCBARRIER(0(ra))
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#ifdef __MIPSEB__
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EX(LONG_S_R, a1, -1(a0), .Llast_fixup)
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#endif
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#ifdef __MIPSEL__
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EX(LONG_S_L, a1, -1(a0), .Llast_fixup)
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#endif
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1: jr ra
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move a2, zero
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.Lsmall_memset:
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beqz a2, 2f
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PTR_ADDU t1, a0, a2
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1: PTR_ADDIU a0, 1 /* fill bytewise */
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R10KCBARRIER(0(ra))
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bne t1, a0, 1b
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sb a1, -1(a0)
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2: jr ra /* done */
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move a2, zero
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END(memset)
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.Lfirst_fixup:
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jr ra
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nop
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.Lfwd_fixup:
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PTR_L t0, TI_TASK($28)
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andi a2, 0x3f
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LONG_L t0, THREAD_BUADDR(t0)
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LONG_ADDU a2, t1
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jr ra
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LONG_SUBU a2, t0
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.Lpartial_fixup:
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PTR_L t0, TI_TASK($28)
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andi a2, LONGMASK
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LONG_L t0, THREAD_BUADDR(t0)
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LONG_ADDU a2, t1
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jr ra
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LONG_SUBU a2, t0
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.Llast_fixup:
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jr ra
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andi v1, a2, LONGMASK
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