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Signed-off-by: Sakari Ailus <sakari.ailus@iki.fi> Acked-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
72 lines
2.0 KiB
Plaintext
72 lines
2.0 KiB
Plaintext
OMAP 3 ISP Device Tree bindings
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===============================
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The DT definitions can be found in include/dt-bindings/media/omap3-isp.h.
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Required properties
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===================
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compatible : must contain "ti,omap3-isp"
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reg : the two registers sets (physical address and length) for the
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ISP. The first set contains the core ISP registers up to
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the end of the SBL block. The second set contains the
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CSI PHYs and receivers registers.
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interrupts : the ISP interrupt specifier
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iommus : phandle and IOMMU specifier for the IOMMU that serves the ISP
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syscon : the phandle and register offset to the Complex I/O or CSI-PHY
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register
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ti,phy-type : 0 -- OMAP3ISP_PHY_TYPE_COMPLEX_IO (e.g. 3430)
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1 -- OMAP3ISP_PHY_TYPE_CSIPHY (e.g. 3630)
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#clock-cells : Must be 1 --- the ISP provides two external clocks,
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cam_xclka and cam_xclkb, at indices 0 and 1,
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respectively. Please find more information on common
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clock bindings in ../clock/clock-bindings.txt.
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Port nodes (optional)
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---------------------
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More documentation on these bindings is available in
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video-interfaces.txt in the same directory.
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reg : The interface:
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0 - parallel (CCDC)
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1 - CSIPHY1 -- CSI2C / CCP2B on 3630;
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CSI1 -- CSIb on 3430
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2 - CSIPHY2 -- CSI2A / CCP2B on 3630;
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CSI2 -- CSIa on 3430
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Optional properties
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===================
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vdd-csiphy1-supply : voltage supply of the CSI-2 PHY 1
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vdd-csiphy2-supply : voltage supply of the CSI-2 PHY 2
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Endpoint nodes
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--------------
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lane-polarities : lane polarity (required on CSI-2)
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0 -- not inverted; 1 -- inverted
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data-lanes : an array of data lanes from 1 to 3. The length can
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be either 1 or 2. (required on CSI-2)
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clock-lanes : the clock lane (from 1 to 3). (required on CSI-2)
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Example
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=======
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isp@480bc000 {
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compatible = "ti,omap3-isp";
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reg = <0x480bc000 0x12fc
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0x480bd800 0x0600>;
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interrupts = <24>;
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iommus = <&mmu_isp>;
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syscon = <&scm_conf 0x2f0>;
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ti,phy-type = <OMAP3ISP_PHY_TYPE_CSIPHY>;
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#clock-cells = <1>;
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ports {
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#address-cells = <1>;
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#size-cells = <0>;
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};
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};
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