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b7c7b05065
The H6 has clock/reset controls in PRCM part, like old SoCs such as H3 and A64. However, the PRCM CCU is rearranged; the register arragement is now similar to the main CCU of H6, and the PRCM now has two APB buses to control -- one is clocked from AHB clock derivde from AR100 clock, the other is clocked from the same mux with AR100 clock. Therefore a new driver is written for it. As there's no official document about the PRCM in H6, all the information are indirectly collected from BSP and parts of the document, and the information source is noted as comments in the driver's source code. If reliable information is provided furtherly, the driver needs to be rechecked. Signed-off-by: Icenowy Zheng <icenowy@aosc.io> Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
25 lines
510 B
C
25 lines
510 B
C
/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Copyright (c) 2017 Icenowy Zheng <icenowy@aosc.xyz>
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*/
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#ifndef _DT_BINDINGS_CLK_SUN50I_H6_R_CCU_H_
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#define _DT_BINDINGS_CLK_SUN50I_H6_R_CCU_H_
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#define CLK_AR100 0
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#define CLK_R_APB1 2
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#define CLK_R_APB1_TIMER 4
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#define CLK_R_APB1_TWD 5
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#define CLK_R_APB1_PWM 6
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#define CLK_R_APB2_UART 7
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#define CLK_R_APB2_I2C 8
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#define CLK_R_APB1_IR 9
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#define CLK_R_APB1_W1 10
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#define CLK_IR 11
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#define CLK_W1 12
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#endif /* _DT_BINDINGS_CLK_SUN50I_H6_R_CCU_H_ */
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