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https://github.com/edk2-porting/linux-next.git
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487d499c67
Delete error handling from the result of a call to platform_get_resource() when the value is immediately passed to devm_ioremap_resource(). Signed-off-by: Belen Sarabia <belensarabia@gmail.com> Signed-off-by: Tejun Heo <tj@kernel.org>
101 lines
2.5 KiB
C
101 lines
2.5 KiB
C
/*
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* SATA glue for Cavium Octeon III SOCs.
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*
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*
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* This file is subject to the terms and conditions of the GNU General Public
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* License. See the file "COPYING" in the main directory of this archive
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* for more details.
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*
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* Copyright (C) 2010-2015 Cavium Networks
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*
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*/
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#include <linux/module.h>
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#include <linux/dma-mapping.h>
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#include <linux/platform_device.h>
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#include <linux/of_platform.h>
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#include <asm/octeon/octeon.h>
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#include <asm/bitfield.h>
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#define CVMX_SATA_UCTL_SHIM_CFG 0xE8
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#define SATA_UCTL_ENDIAN_MODE_BIG 1
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#define SATA_UCTL_ENDIAN_MODE_LITTLE 0
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#define SATA_UCTL_ENDIAN_MODE_MASK 3
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#define SATA_UCTL_DMA_ENDIAN_MODE_SHIFT 8
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#define SATA_UCTL_CSR_ENDIAN_MODE_SHIFT 0
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#define SATA_UCTL_DMA_READ_CMD_SHIFT 12
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static int ahci_octeon_probe(struct platform_device *pdev)
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{
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struct device *dev = &pdev->dev;
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struct device_node *node = dev->of_node;
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struct resource *res;
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void __iomem *base;
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u64 cfg;
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int ret;
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res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
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base = devm_ioremap_resource(&pdev->dev, res);
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if (IS_ERR(base))
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return PTR_ERR(base);
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cfg = cvmx_readq_csr(base + CVMX_SATA_UCTL_SHIM_CFG);
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cfg &= ~(SATA_UCTL_ENDIAN_MODE_MASK << SATA_UCTL_DMA_ENDIAN_MODE_SHIFT);
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cfg &= ~(SATA_UCTL_ENDIAN_MODE_MASK << SATA_UCTL_CSR_ENDIAN_MODE_SHIFT);
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#ifdef __BIG_ENDIAN
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cfg |= SATA_UCTL_ENDIAN_MODE_BIG << SATA_UCTL_DMA_ENDIAN_MODE_SHIFT;
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cfg |= SATA_UCTL_ENDIAN_MODE_BIG << SATA_UCTL_CSR_ENDIAN_MODE_SHIFT;
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#else
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cfg |= SATA_UCTL_ENDIAN_MODE_LITTLE << SATA_UCTL_DMA_ENDIAN_MODE_SHIFT;
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cfg |= SATA_UCTL_ENDIAN_MODE_LITTLE << SATA_UCTL_CSR_ENDIAN_MODE_SHIFT;
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#endif
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cfg |= 1 << SATA_UCTL_DMA_READ_CMD_SHIFT;
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cvmx_writeq_csr(base + CVMX_SATA_UCTL_SHIM_CFG, cfg);
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if (!node) {
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dev_err(dev, "no device node, failed to add octeon sata\n");
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return -ENODEV;
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}
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ret = of_platform_populate(node, NULL, NULL, dev);
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if (ret) {
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dev_err(dev, "failed to add ahci-platform core\n");
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return ret;
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}
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return 0;
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}
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static int ahci_octeon_remove(struct platform_device *pdev)
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{
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return 0;
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}
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static const struct of_device_id octeon_ahci_match[] = {
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{ .compatible = "cavium,octeon-7130-sata-uctl", },
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{},
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};
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MODULE_DEVICE_TABLE(of, octeon_ahci_match);
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static struct platform_driver ahci_octeon_driver = {
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.probe = ahci_octeon_probe,
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.remove = ahci_octeon_remove,
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.driver = {
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.name = "octeon-ahci",
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.of_match_table = octeon_ahci_match,
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},
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};
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module_platform_driver(ahci_octeon_driver);
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MODULE_LICENSE("GPL");
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MODULE_AUTHOR("Cavium, Inc. <support@cavium.com>");
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MODULE_DESCRIPTION("Cavium Inc. sata config.");
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