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https://github.com/edk2-porting/linux-next.git
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cae39d1386
Or else we get lots of variations on this: arch/mips/pci/pci.c:330: warning: type defaults to 'int' in declaration of 'EXPORT_SYMBOL' scattered throughout the build. Signed-off-by: Paul Gortmaker <paul.gortmaker@windriver.com>
405 lines
11 KiB
C
405 lines
11 KiB
C
/*
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* powertv-usb.c
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*
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* Description: ASIC-specific USB device setup and shutdown
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*
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* Copyright (C) 2005-2009 Scientific-Atlanta, Inc.
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* Copyright (C) 2009 Cisco Systems, Inc.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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*
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* Author: Ken Eppinett
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* David Schleef <ds@schleef.org>
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*
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* NOTE: The bootloader allocates persistent memory at an address which is
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* 16 MiB below the end of the highest address in KSEG0. All fixed
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* address memory reservations must avoid this region.
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*/
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#include <linux/kernel.h>
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#include <linux/export.h>
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#include <linux/ioport.h>
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#include <linux/platform_device.h>
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#include <asm/mach-powertv/asic.h>
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#include <asm/mach-powertv/interrupts.h>
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/* misc_clk_ctl1 values */
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#define MCC1_30MHZ_POWERUP_SELECT (1 << 14)
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#define MCC1_DIV9 (1 << 13)
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#define MCC1_ETHMIPS_POWERUP_SELECT (1 << 11)
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#define MCC1_USB_POWERUP_SELECT (1 << 1)
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#define MCC1_CLOCK108_POWERUP_SELECT (1 << 0)
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/* Possible values for clock select */
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#define MCC1_USB_CLOCK_HIGH_Z (0 << 4)
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#define MCC1_USB_CLOCK_48MHZ (1 << 4)
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#define MCC1_USB_CLOCK_24MHZ (2 << 4)
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#define MCC1_USB_CLOCK_6MHZ (3 << 4)
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#define MCC1_CONFIG (MCC1_30MHZ_POWERUP_SELECT | \
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MCC1_DIV9 | \
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MCC1_ETHMIPS_POWERUP_SELECT | \
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MCC1_USB_POWERUP_SELECT | \
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MCC1_CLOCK108_POWERUP_SELECT)
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/* misc_clk_ctl2 values */
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#define MCC2_GMII_GCLK_TO_PAD (1 << 31)
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#define MCC2_ETHER125_0_CLOCK_SELECT (1 << 29)
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#define MCC2_RMII_0_CLOCK_SELECT (1 << 28)
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#define MCC2_GMII_TX0_CLOCK_SELECT (1 << 27)
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#define MCC2_GMII_RX0_CLOCK_SELECT (1 << 26)
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#define MCC2_ETHER125_1_CLOCK_SELECT (1 << 24)
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#define MCC2_RMII_1_CLOCK_SELECT (1 << 23)
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#define MCC2_GMII_TX1_CLOCK_SELECT (1 << 22)
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#define MCC2_GMII_RX1_CLOCK_SELECT (1 << 21)
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#define MCC2_ETHER125_2_CLOCK_SELECT (1 << 19)
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#define MCC2_RMII_2_CLOCK_SELECT (1 << 18)
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#define MCC2_GMII_TX2_CLOCK_SELECT (1 << 17)
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#define MCC2_GMII_RX2_CLOCK_SELECT (1 << 16)
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#define ETHER_CLK_CONFIG (MCC2_GMII_GCLK_TO_PAD | \
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MCC2_ETHER125_0_CLOCK_SELECT | \
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MCC2_RMII_0_CLOCK_SELECT | \
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MCC2_GMII_TX0_CLOCK_SELECT | \
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MCC2_GMII_RX0_CLOCK_SELECT | \
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MCC2_ETHER125_1_CLOCK_SELECT | \
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MCC2_RMII_1_CLOCK_SELECT | \
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MCC2_GMII_TX1_CLOCK_SELECT | \
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MCC2_GMII_RX1_CLOCK_SELECT | \
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MCC2_ETHER125_2_CLOCK_SELECT | \
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MCC2_RMII_2_CLOCK_SELECT | \
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MCC2_GMII_TX2_CLOCK_SELECT | \
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MCC2_GMII_RX2_CLOCK_SELECT)
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/* misc_clk_ctl2 definitions for Gaia */
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#define FSX4A_REF_SELECT (1 << 16)
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#define FSX4B_REF_SELECT (1 << 17)
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#define FSX4C_REF_SELECT (1 << 18)
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#define DDR_PLL_REF_SELECT (1 << 19)
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#define MIPS_PLL_REF_SELECT (1 << 20)
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/* Definitions for the QAM frequency select register FS432X4A4_QAM_CTL */
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#define QAM_FS_SDIV_SHIFT 29
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#define QAM_FS_MD_SHIFT 24
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#define QAM_FS_MD_MASK 0x1f /* Cut down to 5 bits */
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#define QAM_FS_PE_SHIFT 8
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#define QAM_FS_DISABLE_DIVIDE_BY_3 (1 << 5)
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#define QAM_FS_ENABLE_PROGRAM (1 << 4)
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#define QAM_FS_ENABLE_OUTPUT (1 << 3)
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#define QAM_FS_SELECT_TEST_BYPASS (1 << 2)
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#define QAM_FS_DISABLE_DIGITAL_STANDBY (1 << 1)
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#define QAM_FS_CHOOSE_FS (1 << 0)
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/* Definitions for fs432x4a_ctl register */
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#define QAM_FS_NSDIV_54MHZ (1 << 2)
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/* Definitions for bcm1_usb2_ctl register */
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#define BCM1_USB2_CTL_BISTOK (1 << 11)
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#define BCM1_USB2_CTL_PORT2_SHIFT_JK (1 << 7)
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#define BCM1_USB2_CTL_PORT1_SHIFT_JK (1 << 6)
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#define BCM1_USB2_CTL_PORT2_FAST_EDGE (1 << 5)
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#define BCM1_USB2_CTL_PORT1_FAST_EDGE (1 << 4)
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#define BCM1_USB2_CTL_EHCI_PRT_PWR_ACTIVE_HIGH (1 << 1)
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#define BCM1_USB2_CTL_APP_PRT_OVRCUR_IN_ACTIVE_HIGH (1 << 0)
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/* Definitions for crt_spare register */
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#define CRT_SPARE_PORT2_SHIFT_JK (1 << 21)
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#define CRT_SPARE_PORT1_SHIFT_JK (1 << 20)
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#define CRT_SPARE_PORT2_FAST_EDGE (1 << 19)
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#define CRT_SPARE_PORT1_FAST_EDGE (1 << 18)
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#define CRT_SPARE_DIVIDE_BY_9_FROM_432 (1 << 17)
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#define CRT_SPARE_USB_DIVIDE_BY_9 (1 << 16)
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/* Definitions for usb2_stbus_obc register */
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#define USB_STBUS_OBC_STORE32_LOAD32 0x3
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/* Definitions for usb2_stbus_mess_size register */
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#define USB2_STBUS_MESS_SIZE_2 0x1 /* 2 packets */
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/* Definitions for usb2_stbus_chunk_size register */
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#define USB2_STBUS_CHUNK_SIZE_2 0x1 /* 2 packets */
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/* Definitions for usb2_strap register */
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#define USB2_STRAP_HFREQ_SELECT 0x1
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/*
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* USB Host Resource Definition
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*/
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static struct resource ehci_resources[] = {
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{
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.parent = &asic_resource,
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.start = 0,
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.end = 0xff,
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.flags = IORESOURCE_MEM,
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},
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{
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.start = irq_usbehci,
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.end = irq_usbehci,
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.flags = IORESOURCE_IRQ,
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},
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};
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static u64 ehci_dmamask = 0xffffffffULL;
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static struct platform_device ehci_device = {
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.name = "powertv-ehci",
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.id = 0,
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.num_resources = 2,
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.resource = ehci_resources,
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.dev = {
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.dma_mask = &ehci_dmamask,
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.coherent_dma_mask = 0xffffffff,
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},
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};
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static struct resource ohci_resources[] = {
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{
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.parent = &asic_resource,
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.start = 0,
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.end = 0xff,
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.flags = IORESOURCE_MEM,
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},
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{
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.start = irq_usbohci,
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.end = irq_usbohci,
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.flags = IORESOURCE_IRQ,
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},
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};
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static u64 ohci_dmamask = 0xffffffffULL;
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static struct platform_device ohci_device = {
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.name = "powertv-ohci",
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.id = 0,
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.num_resources = 2,
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.resource = ohci_resources,
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.dev = {
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.dma_mask = &ohci_dmamask,
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.coherent_dma_mask = 0xffffffff,
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},
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};
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static unsigned usb_users;
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static DEFINE_SPINLOCK(usb_regs_lock);
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/*
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*
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* fs_update - set frequency synthesizer for USB
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* @pe_bits Phase tap setting
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* @md_bits Coarse selector bus for algorithm of phase tap
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* @sdiv_bits Output divider setting
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* @disable_div_by_3 Either QAM_FS_DISABLE_DIVIDE_BY_3 or zero
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* @standby Either QAM_FS_DISABLE_DIGITAL_STANDBY or zero
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*
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* QAM frequency selection code, which affects the frequency at which USB
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* runs. The frequency is calculated as:
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* 2^15 * ndiv * Fin
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* Fout = ------------------------------------------------------------
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* (sdiv * (ipe * (1 + md/32) - (ipe - 2^15)*(1 + (md + 1)/32)))
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* where:
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* Fin 54 MHz
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* ndiv QAM_FS_NSDIV_54MHZ ? 8 : 16
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* sdiv 1 << (sdiv_bits + 1)
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* ipe Same as pe_bits
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* md A five-bit, two's-complement integer (range [-16, 15]), which
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* is the lower 5 bits of md_bits.
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*/
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static void fs_update(u32 pe_bits, int md_bits, u32 sdiv_bits,
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u32 disable_div_by_3, u32 standby)
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{
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u32 val;
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val = ((sdiv_bits << QAM_FS_SDIV_SHIFT) |
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((md_bits & QAM_FS_MD_MASK) << QAM_FS_MD_SHIFT) |
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(pe_bits << QAM_FS_PE_SHIFT) |
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QAM_FS_ENABLE_OUTPUT |
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standby |
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disable_div_by_3);
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asic_write(val, fs432x4b4_usb_ctl);
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asic_write(val | QAM_FS_ENABLE_PROGRAM, fs432x4b4_usb_ctl);
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asic_write(val | QAM_FS_ENABLE_PROGRAM | QAM_FS_CHOOSE_FS,
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fs432x4b4_usb_ctl);
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}
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/*
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* usb_eye_configure - for optimizing the shape USB eye waveform
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* @set: Bits to set in the register
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* @clear: Bits to clear in the register; each bit with a one will
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* be set in the register, zero bits will not be modified
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*/
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static void usb_eye_configure(u32 set, u32 clear)
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{
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u32 old;
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old = asic_read(crt_spare);
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old |= set;
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old &= ~clear;
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asic_write(old, crt_spare);
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}
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/*
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* platform_configure_usb - usb configuration based on platform type.
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*/
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static void platform_configure_usb(void)
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{
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u32 bcm1_usb2_ctl_value;
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enum asic_type asic_type;
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unsigned long flags;
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spin_lock_irqsave(&usb_regs_lock, flags);
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usb_users++;
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if (usb_users != 1) {
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spin_unlock_irqrestore(&usb_regs_lock, flags);
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return;
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}
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asic_type = platform_get_asic();
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switch (asic_type) {
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case ASIC_ZEUS:
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fs_update(0x0000, -15, 0x02, 0, 0);
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bcm1_usb2_ctl_value = BCM1_USB2_CTL_EHCI_PRT_PWR_ACTIVE_HIGH |
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BCM1_USB2_CTL_APP_PRT_OVRCUR_IN_ACTIVE_HIGH;
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break;
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case ASIC_CRONUS:
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case ASIC_CRONUSLITE:
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usb_eye_configure(0, CRT_SPARE_USB_DIVIDE_BY_9);
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fs_update(0x8000, -14, 0x03, QAM_FS_DISABLE_DIVIDE_BY_3,
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QAM_FS_DISABLE_DIGITAL_STANDBY);
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bcm1_usb2_ctl_value = BCM1_USB2_CTL_EHCI_PRT_PWR_ACTIVE_HIGH |
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BCM1_USB2_CTL_APP_PRT_OVRCUR_IN_ACTIVE_HIGH;
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break;
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case ASIC_CALLIOPE:
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fs_update(0x0000, -15, 0x02, QAM_FS_DISABLE_DIVIDE_BY_3,
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QAM_FS_DISABLE_DIGITAL_STANDBY);
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switch (platform_get_family()) {
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case FAMILY_1500VZE:
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break;
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case FAMILY_1500VZF:
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usb_eye_configure(CRT_SPARE_PORT2_SHIFT_JK |
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CRT_SPARE_PORT1_SHIFT_JK |
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CRT_SPARE_PORT2_FAST_EDGE |
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CRT_SPARE_PORT1_FAST_EDGE, 0);
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break;
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default:
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usb_eye_configure(CRT_SPARE_PORT2_SHIFT_JK |
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CRT_SPARE_PORT1_SHIFT_JK, 0);
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break;
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}
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bcm1_usb2_ctl_value = BCM1_USB2_CTL_BISTOK |
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BCM1_USB2_CTL_EHCI_PRT_PWR_ACTIVE_HIGH |
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BCM1_USB2_CTL_APP_PRT_OVRCUR_IN_ACTIVE_HIGH;
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break;
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case ASIC_GAIA:
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fs_update(0x8000, -14, 0x03, QAM_FS_DISABLE_DIVIDE_BY_3,
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QAM_FS_DISABLE_DIGITAL_STANDBY);
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bcm1_usb2_ctl_value = BCM1_USB2_CTL_BISTOK |
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BCM1_USB2_CTL_EHCI_PRT_PWR_ACTIVE_HIGH |
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BCM1_USB2_CTL_APP_PRT_OVRCUR_IN_ACTIVE_HIGH;
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break;
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default:
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pr_err("Unknown ASIC type: %d\n", asic_type);
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bcm1_usb2_ctl_value = 0;
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break;
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}
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/* turn on USB power */
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asic_write(0, usb2_strap);
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/* Enable all OHCI interrupts */
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asic_write(bcm1_usb2_ctl_value, usb2_control);
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/* usb2_stbus_obc store32/load32 */
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asic_write(USB_STBUS_OBC_STORE32_LOAD32, usb2_stbus_obc);
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/* usb2_stbus_mess_size 2 packets */
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asic_write(USB2_STBUS_MESS_SIZE_2, usb2_stbus_mess_size);
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/* usb2_stbus_chunk_size 2 packets */
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asic_write(USB2_STBUS_CHUNK_SIZE_2, usb2_stbus_chunk_size);
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spin_unlock_irqrestore(&usb_regs_lock, flags);
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}
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static void platform_unconfigure_usb(void)
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{
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unsigned long flags;
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spin_lock_irqsave(&usb_regs_lock, flags);
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usb_users--;
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if (usb_users == 0)
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asic_write(USB2_STRAP_HFREQ_SELECT, usb2_strap);
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spin_unlock_irqrestore(&usb_regs_lock, flags);
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}
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/*
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* Set up the USB EHCI interface
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*/
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void platform_configure_usb_ehci()
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{
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platform_configure_usb();
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}
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EXPORT_SYMBOL(platform_configure_usb_ehci);
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/*
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* Set up the USB OHCI interface
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*/
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void platform_configure_usb_ohci()
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{
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platform_configure_usb();
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}
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EXPORT_SYMBOL(platform_configure_usb_ohci);
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/*
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* Shut the USB EHCI interface down
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*/
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void platform_unconfigure_usb_ehci()
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{
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platform_unconfigure_usb();
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}
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EXPORT_SYMBOL(platform_unconfigure_usb_ehci);
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/*
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* Shut the USB OHCI interface down
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*/
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void platform_unconfigure_usb_ohci()
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{
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platform_unconfigure_usb();
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}
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EXPORT_SYMBOL(platform_unconfigure_usb_ohci);
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/**
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* platform_devices_init - sets up USB device resourse.
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*/
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int __init platform_usb_devices_init(struct platform_device **ehci_dev,
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struct platform_device **ohci_dev)
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{
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*ehci_dev = &ehci_device;
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ehci_resources[0].start = asic_reg_phys_addr(ehci_hcapbase);
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ehci_resources[0].end += ehci_resources[0].start;
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*ohci_dev = &ohci_device;
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ohci_resources[0].start = asic_reg_phys_addr(ohci_hc_revision);
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ohci_resources[0].end += ohci_resources[0].start;
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return 0;
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}
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